Schematic tools in use

Posted by mark_laing Mar 30, 2009

Hi all

 

Generic access to schematic data traditionally was done through schematic EDIF files. However support from different vendors for this format is not consistent and invariably this output is licensed meaning not all users have access to it. I am interested to know which schematic tools people use and what types of ASCII schematic or ASCII netlist data they can create with a standard schematic tool base license.

 

Manufacturing organizations typically use the layout data for the PCB assembly and may have access to a searchable PDF but intelligent schematic or netlist data can improve the data flow in to manufacturing. The challenge is getting access to the schematic data so it can be leveraged outside of the design community.

 

Thanks

 

Mark

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Stencils and Step Stencils

Posted by mark_laing Mar 11, 2009

Hi all

 

I would like to hear from anyone that is involved in the creation of stencil data from both a design perspective and also from the manufacturing perspective.

 

The Stencil is a metal plate that is used to screen solder paste on to a PCB at the start of the assembly process.

 

A standard stencil has a uniform thickness across it. A Step Stencil has variations in thickness across the stencil that allow for adjustments in the paste volume for specific areas of the board.

 

Thanks

 

Mark

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Schematic design analysis

Posted by mark_laing Nov 26, 2008

I am interested to hear from schematic designers on the types of analysis they perform or would like to perform on schematic data. A significant amount of physical analysis is perfromed at various stages of the physical layout but I am interested to know what types of analysis is being performed or needs to be performed at the schematic stage prior to the layout being started.

 

Thanks

 

 

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I had the opportunity to present a paper at the Mentor U2U in Santa Clara on Improving Yields with Advanced DFT. The paper is available from the Mentor web site if you would like to view it.

 

I had a number of questions afterwards from different customers asking about Design For Test guidelines, specifically in the area of boundary scan.

 

 

I am interested to know how you are incorporating boundary scan in to your designs, which boundary scan tool you are using and what feedback mechanism you use to work with Test Engineering to accommodate their requirements.

 

 

Thanks

 

 

Mark

 

 

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In-Circuit Test (ICT) has always relied on a bed of nails fixture as an interface between the PCB and the test machine. Originally 100 mil probes were used to make contat with the PCB given the standard pin pitch of through hole components was 100 mil. Then surface mount components appeared and smaller probes were needed, introducing 75 mil and then 50 mil probes. Now even 39 mil probes are being used.

 

A couple of years ago, Agilent Technologies introduced a new technique that allowed greater probe access to a PCB called Bead Probe. Here a solder bead can be added to any point along a trace which is the accessed with a flat head test probe to make electrical contact with the PCB. I am interested to know if users are aware of this technique, whether they have implemented it and if so how easy or difficult it was to introduce it.

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For many years, the staple of manufacturing process verification was In-circuit Test (ICT). Now with limited test access Test Engineers are looking to supplement ICT with other technologies such as Boundary Scan, Flying Probe Test, Automatic Optical Inspection and Automatic X-Ray Inspection to name a few. Being able to effectively manage these multiple technologies has been an area I have been interested in for a number of years.

 

I would be interested to hear how Test Engineers are working in this area. What tools they you using, what challenges they you finding and what areas you feel are not being served well with existing solutions.

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