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Community Description

Welcome to the ASIC/FPGA Design Community !

ASICs and FPGAs have progressed tremendously with complex FPGAs now requiring ASIC-like design methodologies. The expansion of HDLs from VHDL and Verilog to SystemVerilog has further fueled the necessity for sophisticated design methodologies. Additionally, raising the abstraction level for design and synthesis from RTL to Electronic System Level (ESL) with languages such as C/C++ and SystemC has enabled engineers to understand the combined impact of the hardware and software architecture on system power, performance and functionality early in the design project. It is with these needs that we have created this ASIC/FPGA community to facilitate designers in communicating, collaborating, comparing, and occasionally commiserating, on ASIC and FPGA design. We welcome all of your input.

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General 33 1 0
Design and Synthesis 51 2  
Radiation Tolerant FPGA Design 16 1  

Recent Content

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Subject Author
Re: how to connect ahb vip slave signals to the dut in axi2ahb num slave bridge project 2 weeks ago in ASIC/FPGA Design by durgaashok.bavirsetty durgaashok.bavirsetty
Question on Power aware simulation using UPF ? 1 month ago in Design and Synthesis by k.kumar k.kumar
Re: Can i add the .vcd file generated from Questasim as an input to Precision RTL ? 1 month ago in Design and Synthesis by k.kumar k.kumar
Register Now!  U2U San Jose - April 10, 2014 1 month ago in ASIC/FPGA Design by jennifer_chausse jennifer_chausse
Re: Warning while opening component instance at HDL Author. 4 months ago in Design and Synthesis by slesarevas slesarevas
Dangling nets 8 months ago in ASIC/FPGA Design by chaitanya.kotagiri chaitanya.kotagiri
Re: Precision 2009a.76 Crashing during synthesis ? 9 months ago in Design and Synthesis by Hans Hans
Re: precision_rtl crashes during rtl optimization 9 months ago in Design and Synthesis by Guy Guy
Re: Unable to launch DesignChecker from HDL Designer Series 2012.1 1 year ago in Design and Synthesis by Guy Guy
Re: Where is information on Precision Hi-Rel? 1 year ago in Radiation Tolerant FPGA Design by Guy Guy
Re: how to print the wave file? 1 year ago in General by jerry.hobbs jerry.hobbs
Re: flow of icstudio 1 year ago in General by christian_parg christian_parg
Re: AutoCells on Solaris 10 1 year ago in General by christian_parg christian_parg
Re: Mentor Static Timing analysis Tool 1 year ago in General by christian_parg christian_parg
Process Parameters in 90nm CMOS 1 year ago in ASIC/FPGA Design by 10mecv28 10mecv28
Re: precision synthesis gives "No such Package vpkg is visible" 1 year ago in Design and Synthesis by Hans Hans
Re: Moduleware D F-F Initialize,  specifing the value 1 year ago in Design and Synthesis by Hans Hans
Re: FASTSCAN Fault Simulation! 1 year ago in Design and Synthesis by Guy Guy
Re: Leonardo Spectrum Synthesis using Universal Gates 1 year ago in Design and Synthesis by Guy Guy
FASTSCAN Fault Simulation! 1 year ago in ASIC/FPGA Design by cza0011 cza0011
Re: Difficulties in mapping component 1 year ago in Design and Synthesis by Guy Guy
Re: locked source file 2 years ago in General by Guy Guy
U2U 2012 Santa Clara - Registration is Open! 2 years ago in ASIC/FPGA Design by jennifer_chausse jennifer_chausse
Re: PS & altasmi_parallel on Cyclone III - unknown library 2 years ago in Design and Synthesis by Guy Guy
Re: Precision & Cyclone II illegal altclkctrl inferring 2 years ago in Design and Synthesis by dipling dipling
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What design language do you primarily use? VHDL (61%) Verilog (14%) Mixed VHDL/Verilog (7%) SystemVerilog (9%) SystemC (2%) ANSI C++ (7%) Votes 57

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