Mentor Graphics Communities : All Content - General

how to print the wave file?

community_admin@mentor.com — Wed, 12 Sep 2012 16:02:11 GMT

how to print the wave file?

flow of icstudio

community_admin@mentor.com — Tue, 09 Dec 2008 10:29:43 GMT

Dear All, I am encountring a problem while working with icstudio. With icstudio after initializing necessary library and cell I am facing problem in simulating the schematic design in da_ic.

The errors I am getting is " not defined PCH and NCH". If i am missing certain files to include then please let me know.

Thanks

AutoCells on Solaris 10

community_admin@mentor.com — Fri, 01 Apr 2011 08:27:48 GMT

Hi folks,

is there any guy out there got AutoCells (2004.3 with patch p0247) working on Solaris 10 (SPARC)?

We need this tools within a PDK for P&R including Clock Tree Synthesis. Unfortunately the CTS feature is not included in ICassemble.

Sure AutoCells is designed for Solaris 7-9, but should be upward compatible.

The error message spat out is:

libc internal error: _rmutex_unlock: rmutex not held

Google wasn't really helpful.

Kind regards

Kay

Mentor Static Timing analysis Tool

community_admin@mentor.com — Mon, 03 Jan 2011 10:54:30 GMT

Hello,

I'm used to Modelsim for simulation. I'm wondering if Mentor has tools for STA like PrimeTime that would take netlist, SDF and timing constraints for analysis.

I've had a quick glance at their website and I've found ICX /TAU which is more board level analysis.

Thanks for anwers.

Regards,

Sébastien

locked source file

community_admin@mentor.com — Thu, 22 Mar 2012 09:32:17 GMT

Hello guys,

I am using HDL-designer when I try to open source file code , it is appear in the bottom bar but I can not show it .

And when I try to open the file from C drive , it create lck file .

Please , I need your help

No VHDL Templates for HDL Designer

community_admin@mentor.com — Tue, 24 Jan 2012 22:07:00 GMT

I am running HDL Designer for Windows 7 64 bit. Every time I try to create a block using with combined VHDL coding, the default template never shows up when the coding window opens and none of the changes I make to the block ever save. Does anyone have any idea what the problem might be?

*TEST POST -- PLEASE DISREGARD **

community_admin@mentor.com — Thu, 15 Sep 2011 17:40:58 GMT

This post is to help us troubleshoot a small issue in the communities. Please disregard. thanks.

Copied 2568 link from actual doc page into editor: http://communities.mentor.com/mgcx/docs/DOC-2568

Typed 2568 link into editor: http://communities.mentor.com/mgcx/docs/DOC-2568

Pasted 2568 link into Attach Link: http://communities.mentor.com/mgcx/docs/DOC-2568

Copied 2645 link into editor: http://communities.mentor.com/mgcx/docs/DOC-2645

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Pasted 2645 link into Attach Link: http://communities.mentor.com/mgcx/docs/DOC-2645

Copied new doc link into editor: http://communities.mentor.com/mgcx/docs/DOC-1629

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Pasted new doc link into Attach Link: http://communities.mentor.com/mgcx/docs/DOC-1629

Top M2M Manufacturers

community_admin@mentor.com — Mon, 20 Dec 2010 09:53:23 GMT

Hi everyone.

Who are the leading M2M manufacturer's?

I really don't know if this is where i should ask about this question. But I just posted it here anyway.

Please advise or refer me to any links to my inquiry.

Thanks.

Glenn

Determine critical path of circuit

community_admin@mentor.com — Thu, 21 Oct 2010 07:17:43 GMT

Can anyone please tell me if it is possible to find critical path of a circuit using only ModelSIM? I have a combinational logic block with 8 inputs and want to simulate all possible input combinations to see which takes the maximum time.

Are there any commands/menu options available for that? I searched the internet and could not find any info.

Thanks

Handel-c with Altera Cyclone II and III

community_admin@mentor.com — Thu, 29 Jul 2010 19:33:14 GMT

I'm a green student to both Handel-c and FPGA. My question is, Can I use Handel-c to program Altera Cyclone II familiy and Cyclone III FPGA's.

Help for the driver of RC240 in Windows 7 (64-bits)

community_admin@mentor.com — Thu, 22 Apr 2010 11:47:25 GMT

Hi,

Any one knew how to install the FPGA develop board (RC240) in Windows 7 (64bits) system? the original driver in the DK5 is suit for 32bits windows system. Many thanks for helps!

.noisetran

community_admin@mentor.com — Tue, 22 Dec 2009 17:22:29 GMT

Problem statement:

Track and hold Circuit: 1.5v DC ideal voltage source connected to a 1pF capacitor through a CMOS (transmission gate) switch.

Sampling frequency 100nS.

Transient sim run for 50 clock cycles and the average of the hold state noise voltage

taken over these 50 cycles.

Run eldo noisetran statement as follows,

.noisetran fmin=1 fmax=1e9 nbrun=50 nmod=2

(also disabled flicker noise components in my Bsim3v3 model files)

The idea is to observe only the thermal noise.

One would expect the output noise on the capacitor to be
KT/c of 1pF at room temp which would be 64uV or close.

The rms out of the simulator gives me 52uV.

Dosent make sense.

Can anyone who knows how to interpret .noisetran sims comment on this.

Thanks,

ashu

Merge 2 layers into 1

community_admin@mentor.com — Wed, 23 Dec 2009 18:37:12 GMT

I am trying to extract a layout using calibre, however the current layout has 'active' and 'n/p select' masks, while the calibre file uses separate 'P+/N+ S/D' implants. So trying to match the existing layouts GDS numbers to layers in calibre is difficult. What needs to happen is the 'P+ S/D' layer needs to be linked to the 'active' and 'pselect' layers in the original layout and similarly for the 'N+ S/D' layers they need to be linked to the 'active' and 'nselect' layers.

Can someone tell me if this is the correct approach and if so how to do it. If not what should I be doing?

Library import

community_admin@mentor.com — Mon, 23 Nov 2009 22:42:45 GMT

I have some libraries I downloaded from Luminary Micro for the micro controllers they produce. I tried to import them put they would not import. I noticed that the had file formats as listed below.

.pt4

.pd4

.ln4

.ld4

What do I need to do in order to import these files into PADs?

How to add user-made libraries in other projects?

community_admin@mentor.com — Sat, 21 Nov 2009 19:26:33 GMT

Hello all,

I am new to HDL designer series. I have created some VHDL files (basic blocks) in one project, created symbols for them. and then used those symbols in the block diagram of another project, but this project does not get compiled and says it couldn't find those files, though I have added my earlier project library in this project. When I create a block diagram in the same project it does get compiled.

Can anybody tell me how to add certain use-made library to another projects?

Converting Flopack compact models to a format that Icepak can use

community_admin@mentor.com — Fri, 06 Nov 2009 19:19:59 GMT

Anyone knows if there is a code available that can achieve it? A few of our customers use Icepak which can't use DELPHI models created in Flopack. We would like to avoid the expense to purchase Icepak just to meet the demands of a very smal % of our customers. If no such codes, what are the other options that are most cost effective than purchasing Icepak?

Thanks in advance!

Trouble interpretting .noisetran simulation results in eldo

community_admin@mentor.com — Thu, 05 Nov 2009 16:15:00 GMT

Hi Folks,

Problem statement:

Track and hold Circuit: 1.5v DC ideal voltage source connected to a 1pF capacitor through a CMOS (transmission gate) switch.

Sampling frequency 100nS.

Transient sim run for 50 clock cycles and the average of the hold state noise voltage

taken over these 50 cycles.

Run eldo noisetran statement as follows,

.noisetran fmin=1 fmax=1e9 nbrun=50 nmod=2

(also disabled flicker noise components in my Bsim3v3 model files)

The idea is to observe only the thermal noise.

One would expect the output noise on the capacitor to be
KT/c of 1pF at room temp which would be 64uV or close.

The rms out of the simulator gives me 52uV.

Dosent make sense.

Can anyone who knows how to interpret .noisetran sims comment on this.

Thanks,

Imu

failed to open the TCP port number in the license

community_admin@mentor.com — Tue, 03 Nov 2009 15:52:26 GMT

Dear all,

I have obtained the following message when i tried to start the icflow license daemon at 1717 tcp port number on a Redhat Enterprise linux 4 AS.

"failed to open the TCP port number in the license"

Everything is okay when i use the Redhat Enterprise linux 3 AS operating system.

I tried to disable firewall but it did not resolve the problem

Any ideas please

Regards

Could not invoke eldo and ezwave from design architect

community_admin@mentor.com — Wed, 21 Oct 2009 15:25:50 GMT

Dear all,

I have installed and configured correctly both AMS and IC flow package.
When i only configure MGC_AMS_HOME environement variable to point to AMS install directory, eldo and ezwave work perfectly.
When i only configure MGC_HOME environement variable to point to IC Flow install directory, da_ic works also perfectly.

But when i configure both MGC_HOME and MGC_AMS_HOME environement variables at the same time da_ic could not start : and an error message is obtained

/MGC/2006.1_rhx86linux/icflow_home/bin/da_ic: line 1: /MGC/2006.1_rhx86linux/icflow_home/ixl/bin/resolve_mgc_path_ic: No such file or directory

Any idea please
Regards

OVM and Questa

community_admin@mentor.com — Fri, 04 Sep 2009 15:11:53 GMT

Hi all

We are just starting with SystemVerilog, therefore with OVM, and Questa. To start we make a new project, a new library and a new SV file like the following.

class test extends ovm_void;

endclass: test

However when we try to compile this, we get this error:

# ** Error: D:/projects/Math2mat/implementation/questa/test/test.sv(1): near "ovm_void": syntax error, unexpected "IDENTIFIER"

# ** Error: D:/projects/Math2mat/implementation/questa/test/test.sv(1): Error in class extension specification.

As a next step we tried to do this:

`include "ovm_pkg.sv"

class test extends ovm_void;

endclass: test

What in turn generates other errors:

regarding fpga emulators

community_admin@mentor.com — Wed, 26 Aug 2009 21:42:04 GMT

Has anybody worked with FPGA emulators? i came across how "Veloce" (fpga emulator from mentor Graphics) is being adopted by many companies. wanted to know how this compares with Precision Synthesis from Mentor. Any information on this?

Thanks

Is Platform Express still available?

community_admin@mentor.com — Wed, 18 Mar 2009 07:01:16 GMT

Thanks.

LinkedIn Poll: Where is the greatest HW/SW register interface pain?

community_admin@mentor.com — Tue, 07 Apr 2009 21:33:58 GMT

Read about the LinkedIn poll, and find a link to it at...

http://www.registerbits.com/poll-where-is-the-greatest-hwsw-register-interface-pain

So far the biggest pain is keeping the firmware, RTL, HW verification, and documentation all syncronized.

Level-triggered vs. Edge-triggered interrupts?

community_admin@mentor.com — Fri, 13 Mar 2009 04:47:26 GMT

Got an opinion on level/edge interrupts? Add to the discussion at http://www.registerbits.com/level-triggered-vs-edge-triggered-interrupts

Cell text edit in hdl_designer

community_admin@mentor.com — Thu, 22 Jan 2009 00:22:15 GMT

Hi all,

I apologise for the simplicity of this question as it may seem.

How ever, we have a problem where we can add text in a cell, as in a port description, but if we try and edit it afterwards (with a double click) we have no luck, other than being able to overwrite the whole string, which is somewhat annoying.

We have one member in our team that is able to edit previously entered text so there must be some setting to enable this.

Any Ideas what we have to chage to enable this, its bound to be simple but we can't find it.

Thanks

Trev

Help with simulations in ELDO

community_admin@mentor.com — Wed, 10 Dec 2008 13:49:47 GMT

Hello! my name is Edwin and I'm triyng to do some simulations more faster using ELDO, the question is, if I have 4 processor in my computer, How do I to use all these processors to run the simulation?

For example, for run the PEX (parasitics extraction) in Calibre, there is a place to choose if I want to run with 01 processor or more than one.

If anyone knows the answer please send me an email (edwin_sanchez@yahoo.com)

thanks

DesignWave and HDL Designer/ModelSim

community_admin@mentor.com — Thu, 11 Dec 2008 11:44:01 GMT

Dear all,

I'm using FPGA Advantage 7.2 (including HDL Designer

2005.3 and ModuleWare 1.7) for a FPGA design. I wanted to use the

built-in DesignWave module to generate stimuli in order to test a

design. I followed the documentation's tutorial but it didn't work for

me. What I did was:

Automatically generated a testbench including a tester block
double clicked on the tester block and chose Registered view -> DesignWave Waveform Database
Drawed waveforms for the tester signals representing my stimuli
Saved the waveforms and the testbench design and started the ModelSim Flow

When I simulate my design the sginals don't show any activity.

Examining the generated HDL code of the tester block I find comments

-- ModuleWare code(v1.7) for port 'CLK' of type 'clk'

but there isn't any code.

Could you imagine a reason for that?

Thanks for any hints or suggestions!

vhdl-ams code error

community_admin@mentor.com — Wed, 22 Oct 2008 09:24:32 GMT

what type of error is this?


Error: The characteristic number (24) does not match the number of scalar equations (10) +LRM section 12.6.6

plz help me.

Anyone have design experience with Inventra's M8052 8-bit Microcontroller?

community_admin@mentor.com — Wed, 24 Sep 2008 20:59:26 GMT

I am creating a microcontroller system with the M8052. Has anyone had any experience or other references using this IP other than the user guides that came with this package?

I am having difficulty interfacing CoreGen memory modules from Xilinx during the simulation. Has anyone interfaced BRAM blocks with this IP?

Thanks,

Hector

Requirements Tracing

community_admin@mentor.com — Mon, 12 May 2008 06:04:09 GMT

Hi Folks,

Mentor recently introduced a new product called ReqTracer that allows you to trace requirements all the way from the system level down to HDL design files and verification results. New safety critical standards, like DO-254, have objectives related to tracing requirements down to design and verification artifacts. I'm curious how folks are addressing this today. What tools and methods are you using? Do you currently trace requirements all the way down to design and verification data?

Thanks

Rex

Mentor Graphics Communities : All Content - General

how to print the wave file?

flow of icstudio

AutoCells on Solaris 10

Mentor Static Timing analysis Tool

locked source file

No VHDL Templates for HDL Designer

***TEST POST -- PLEASE DISREGARD ****

Top M2M Manufacturers

Determine critical path of circuit

Handel-c with Altera Cyclone II and III

Help for the driver of RC240 in Windows 7 (64-bits)

.noisetran

Merge 2 layers into 1

Library import

How to add user-made libraries in other projects?

Converting Flopack compact models to a format that Icepak can use

Trouble interpretting .noisetran simulation results in eldo

failed to open the TCP port number in the license

Could not invoke eldo and ezwave from design architect

OVM and Questa

regarding fpga emulators

Is Platform Express still available?

LinkedIn Poll: Where is the greatest HW/SW register interface pain?

Level-triggered vs. Edge-triggered interrupts?

Cell text edit in hdl_designer

Help with simulations in ELDO

DesignWave and HDL Designer/ModelSim

vhdl-ams code error

Anyone have design experience with Inventra's M8052 8-bit Microcontroller?

Requirements Tracing

*TEST POST -- PLEASE DISREGARD **