Mentor Graphics Communities : All Content - Layout and Routing

Arc routing in Expedition 2005

community_admin@mentor.com — Wed, 08 May 2013 09:29:44 GMT

Hi all,

i am using expedition 2005 . can anyone share how better the arc routing can be done in 2005? i feel very difficult route or edit in arc. it's taking too much time. please help me on this.

Comparison between Mentor expedition 2005 and 2007

community_admin@mentor.com — Tue, 07 May 2013 09:05:50 GMT

Hi all,

right now i am working in expedition 2005.i am planning to change to expedition 2007. could anyone please share comparison between 2005 & 2007 or the improvements or specialities in 2007 version.

Can´t create "target areas"

community_admin@mentor.com — Tue, 23 Apr 2013 18:15:01 GMT

Hello everybody,

does anybody of you have problems to create "target areas" for "route targets". In the documentation it is said that if i want to open the "Target Area Dialog" I should click on the menue button "Route->Target Area" while in route mode. Unfortunately this menue entry is dissabled, and I can´t find out why.

Does anybody have any idea?

Thanks

Greetings

Harald Wojtkowiak

PADS connectivity on Plane Hatch Outline

community_admin@mentor.com — Mon, 22 Apr 2013 14:52:59 GMT

Hi,

I have a design in PADS Layout 9.5 and I'm having issues with verify connectivity.

I have an isolated ground plane hatch outline with a couple of components that have traces which connect to the flooded outline using stitching vias. I'm seeing, however, verify design errors on connectivity reporting that the isolated ground plane is not connected. Further, ratsnest appears to indicate no connectivity between the stitching vias and the plane hatch outline.

The vias thermals are set to flood over and the thermals I setup on other through hole components within the isolated ground are all generated correctly. I've attached a screenshot of the plane hatch outline and circled where the error was being reported.

I feel like I'm missing something here, does anyone have any ideas where the problem might lie???

Greetings,

Darren

2 Layer IR Sensor PCB layout designing

community_admin@mentor.com — Mon, 15 Apr 2013 07:18:27 GMT

Can anyone suggest me what all are the things i need to take care for 2 Layer IR sensor board for EMI and EMC prospective.

thanks,

ECAD/MCAD Collaboration

community_admin@mentor.com — Thu, 11 Apr 2013 18:03:06 GMT

I am curious as to what tools/processes your companies are utilizing to generate 3D PCBs in MCAD. Are any of you familiar with IDF-TO-3D?

Thanks,

Keith

multiple via spans

community_admin@mentor.com — Thu, 28 Mar 2013 14:50:28 GMT

New to Explorer and I need to set up more via spans in the setup parameter for my design.

In the attached picture I have my initial setup for a set of via's and now need to also setup

another set using same via spans (Layer to layer) but they have different size holes and or pads.

When I setup the first via I get an warning..."invalid via span definition & via spanning layers 1 through 2

has already been defined."

Thanks,

John

Beginner with Mentor PCB design sofware

community_admin@mentor.com — Wed, 27 Mar 2013 17:02:07 GMT

Hello,

I worked with a old version of ORCAD by doing simpler designs. Due to the complexity in my new design and the fact that we have already the Mentor tools license (University license), we have decided to pass to Mentor PCB design sofware.

I have already created my own library and I also have created the schematic of my design. Now I have to translate my schematic design to a layout PCB. The thing is that the expedition PCB tool is not so intuitive as I though. I need to understand how to:

-Verify the Layout

-Utilize the Constraint Editor System (CES)

-Route, using both manual/interactive and automatic tools.

Is there any basic tutorial?

I have another issue, when I press the AUTO button in Expedition PCB I get the following message in the output window :

Info: Cannot Auto Route design with Microvia spans because the Advanced Interconnect license is not available.

Is it mean that I have to acquire other license?

Thanks for any help in advance,

Andoni

Starting new PCB layout

community_admin@mentor.com — Mon, 25 Mar 2013 14:37:16 GMT

I'm very new to the expedition world and have a few questions.

I'm starting a design that was perviously designed in Cadence Allegro.

The plan here is to load into expedition a .kyn netlist made manually from the design Allegro ascii netlist. Are

there any converters available to make the job easier? Does anyone have a sample to make sure I have the format

correct?

I have the outline drawn in expedition and have the layers (8) setup. The tool does not let me change the layers 4 and 5 from

signals to power planes. The Plane Assignments button and pull down are in the unusable state.

Also the CES button and pull down are in the unusable state. Maybe because there are no nets in the .pcb yet?

Thanks for any help in advance,

john

Plane Tie leg not visible in gerber

community_admin@mentor.com — Tue, 26 Mar 2013 05:24:28 GMT

Hi All,

When i create the gerber Plane tie leg not visible in Gerber.

Attached file for your reference.

Can anyone help me to solve this.

Thanks,

orcad netlist import to expedition

community_admin@mentor.com — Mon, 17 Sep 2012 08:05:28 GMT

Hi ,

I have a Orcad Capture(V16) schematic. I'd like to use expedition(V2007.9.2) PCB as a routing tool. I need information about the procedure to do that.

i have created a netlist in intergrah but not able to update this to expedition pcb, and also how to assign expedition foot print in orcad capture and how to generate the netlist for expedition PCB.

can any one help me how to sync orcad schematic and expedition pcb.

Thanks in Advance.

OLE exception

community_admin@mentor.com — Wed, 13 Mar 2013 13:27:39 GMT

Have someone seen the cash problem "OLE exception " when switch Layout to routing ? see the attachment. How can I repaire it? It seems the PCB file has proeblem because of some wrong operations.

The version is PAD 9.2.

Thanks.

EE7.9.4 Cell Editor: hidden feature?

community_admin@mentor.com — Sat, 06 Oct 2012 08:52:34 GMT

Hi Mentor,

I started using the EE7.9.4 and immediately I noticed a strange thing.

When I save a cell, Cell Editor performs two write operations. This is evident by looking at the mouse cursor and so Cell Editor takes twice the time to save a cell.

I immediately thought of an error, but after a little investigating I discovered that CE create a new folder under the Central Library with "CCZ" as name.

Practically every time I save a cell, CE create under MyCL/CCZ/CellDBlibs a folder with the same name of the Cell Partition and in this new folder it creates two files; one log and a "cce" ( encrypted ccz )

Here is an image.

What are they? Why can not I find any information in released documentation? Because this function is not optional? What is the new software that needs these files?

I think I can delete the "CCZ" folder but I would like to have some information about.

Best regards

Bolis Bortolo

Why a via cannot be semi-fixed?

community_admin@mentor.com — Thu, 10 Jan 2013 00:20:21 GMT

Hello, Why a via cannot be semi-fixed?

[EE 7.9.4] Pads overlaping

community_admin@mentor.com — Thu, 07 Mar 2013 10:00:48 GMT

Hi!

I have the following question to you, is it possible to overlap two resistors pads in Expedition? I want to achieve the effect as in the attached picture.

Regards,

Krzysztof Sielewicz

Synchronizing Expedition Designs with Orcad Schematics

community_admin@mentor.com — Mon, 18 Feb 2013 06:06:01 GMT

Hi all,

I have schematic in Orcad capture cis and i want to Synchronizing with Expedition PCB.

can any one guide me how to Synchronizing with orcad schematic with expedition PCB and how to cross probing .

Thanks,

Karthik.R

[EE 7.9.4] Netlines viewing

community_admin@mentor.com — Fri, 15 Feb 2013 10:04:43 GMT

Hi!

I have the following question to you, don't you know if it's possible Expedition PCB shows the netlines not from pin to pin, but from hanger to hanger?

Best regards,

Krzysztof Sielewicz

[EE 7.9.4] Problem with moving multiple object

community_admin@mentor.com — Fri, 01 Feb 2013 09:25:09 GMT

Hi!

1) I have the following problem: when I select a group of elements and then try to move them, they get out of the screen and I can't move them back to the board outline area. I suppose that this is a bug, is there any fix for it?

2) Is there a way when using "Circuit move & copy" function to simply move the selected objects by the specified offset? For example I'd like to select a few components and move them by e.g. -100,200 mils.

Regards,

Krzysztof Sielewicz

Modeless commands inop!

community_admin@mentor.com — Mon, 21 Jan 2013 18:17:20 GMT

Greetings;

Setup: Pads 9.4 on Windows XP, Intel core2 Quad CPU Q6600 @ 2.4GHz Good Graphics card for using Solidworks 3D CAD.

Today I started doing some cleanup on a design and my modeless commands do not work in PADS Layout.

Even Windows copy (ctrl C) and paste (ctlr P) are dead. I opened a text editor and copy/paste works there, so it's not Windows.

Specific commands I need today are Shift S, Ctrl R, and Ctrl Q.

Anyone have any ideas as to why and how I fix it?

I rebooted everything with no help. I have run into times where a reboot was needed.

Thanks

Russell Purkey

Connect two pads in a cell to a symbol with only one pin

community_admin@mentor.com — Thu, 17 Jan 2013 06:38:14 GMT

Hello, I have a faston tab component. The simbol created by the librarian have two slots, one per each pin and the cell has two pads. the problem is I want to connect both pins of the cell with only one symbol slot because if I use insert both slots in the schematic is more difficult to understand (this PCB has 20 faston tabs. If I duplicate the number of slots, I will have 40 faston tabs simbols in the schematic ).

In DxDesigner for PADS we used the property SIGNAL and it works but it does not work in Expedition.

Thanks, Oscar

Nets of diff_piar puzzle

community_admin@mentor.com — Sun, 22 Jul 2012 15:03:29 GMT

These days , I found a strange phenomenon,this problem led me stop my work,so I would like to ask ,I paint diff_pair ,give a simple example

,each line through a capacitor ,a differential line through two capacitors.Assume the net in front of the capacitors are :IN_P,IN_N, the net behind

the capacitors are seted to be OUT_P,OUT_N, In schematic they were seted to be diff_pair ,general we want the two diff_pairs should be

independent,however,something happened,afer we set them to be th diff_pairs, OUT_P,OUT_IN will includ IN_P,IN_N, it means that IN_P

will inside in OUT_P, IN_N will inside in OUT_N, the nets OUT_P and IN_P look like the same one,the nets OUT_P and IN_P look like the same one too,

Then I use ANALOG seprate them from each other , and I want to see if I can set them independent, then strange things happened I can set the IN_P and IN_N into a differential pair,

but cannot set OUT_P and OUT_N to be a differential pair.

The tips is” the Electrical NET OUT_P OUT_N is a power net, and it cannot be used to creat the diff pair”. But surely they are not power net at all. What can I DO,Who can help me , thank you ~ ~ ~

Using Topology Type in CES

community_admin@mentor.com — Thu, 27 Dec 2012 17:42:49 GMT

I am setting my topology type to TShape in the CES spreadsheet. When I route the board it lets me route the net without using a T route. I also do a DRC and do not see any indication of an error routing this net serially. I would think it would either force me to route the net as a T or it would list it as a DRC error. Any ideas? Thanks.

constraint editor

community_admin@mentor.com — Fri, 21 Dec 2012 06:43:54 GMT

how the differentials signals are defined in the constraint editor.

Sawtooth Tuning Patterns

community_admin@mentor.com — Mon, 01 Jun 2009 14:52:54 GMT

Hello,

I am interested in understanding some of the use cases or requirements specific to supporting Sawtooth tuning. Today we support these tuning patterns being interactively placed via Smart Utilities Dynamic Tune fuctionality. If anyone is interested in a Video of using Smart Utilities Dynamic Tune to generate Sawtooth patterns, please respond and I will get this posted.

We are thinking about supporting these with a more native/automated tuning methodologies and I would like to understand the use cases requiring these patterns.

The first use case is specific to tuning individual legs of a DiffPair into tolerance. With this use case our understanding is the DiffPair itself will be tuned with normal serpentine tuning patterns and Sawtooth patterns will be used to equalize the length of one leg of a DiffPair to another.

Here are a few bitmap examples of what we are thinking.

Here is another bitmap example:

Is it correct to say that a DiffPair, both legs, when tuned will not use Sawtooth patterns?

I suspect that some single ended nets will require Sawtooth tuning patterns to minimize the self net coupling. Are there any specific use cases that require Sawtooth tuning patterns for single ended nets? Please respond any use cases to ensure we have all of the requirements to support Sawtooth Tuning.

Jerry Suiter

ExpeditionPCB/XtremePCB Product Marketing Manager

Database Integrity Issue, objects outside design area in CAM

community_admin@mentor.com — Tue, 18 Sep 2012 15:41:21 GMT

I'm having an issue where I preview my CAM files and I have some objects on the Top layer that are not seen in the design area to be able to select and delete.

I've tried to export the pcb as ASCII and reimport it hoping to have it scrub the invalid data, but that comes along too.

It looks like a 2D line, so I can't NOT export the lines object.

I've tried to modeless jump to these points, but it doesn't allow it.

I'm using version 9.4

Any ideas how I can fix this?

Thank you

Here is the report file:

ERROR: Drawing on layer Top near (42969.52, -3061.02) (Name: D30791937, Id: 76) has box outside design space

(-13405.22, -3071.37) (-13384.54, -3050.68)

ERROR: Drawing on layer Top near (42969.52, -3061.02) (Name: D32410673, Id: 77) has box outside design space

(-13405.22, -3071.37) (-13384.54, -3050.68)

ERROR: Drawing on layer Top near (43424.25, -3061.02) (Name: D74808640, Id: 78) has box outside design space

(-12950.5, -3071.37) (-12929.81, -3050.68)

ERROR: Drawing on layer Top near (43424.25, -3061.02) (Name: D38371555, Id: 79) has box outside design space

(-12950.5, -3071.37) (-12929.81, -3050.68)

Error: E0103:Invalid attribute values tree, handle c15b070

Error: E0103:Invalid attribute values tree, handle c195a60

Error: E0103:Invalid attribute values tree, handle c19d77c

Error: E0103:Invalid attribute values tree, handle c19d7c0

Error: E0103:Invalid attribute values tree, handle c183e38

Swapping pins in BoardStation RE

community_admin@mentor.com — Wed, 29 Aug 2012 17:13:01 GMT

How can I swap pins in BoardStation RE? I see the "Swap pins" icon when in route mode but it is greyed out. Does anyone know how to use this functionality? Thanks.

Optimal naming of design objects

community_admin@mentor.com — Fri, 17 Aug 2012 11:53:29 GMT

I encourage you to use this link to jump to the discussion I have submitted in Design section on how best match constraints and connectivity objects to get optimal PCB design structure.

http://communities.mentor.com/mgcx/thread/10033

Thanks!

Define net clearance

community_admin@mentor.com — Tue, 07 Aug 2012 11:19:12 GMT

How to define (increase) a clearance around a BATT signal (pads,traces,vias,planes,all... ) in all layers. See pic attached. Thanks in advance

Ricardo

Layout of a Resistor

community_admin@mentor.com — Tue, 24 Jul 2012 17:35:02 GMT

Hi...

I am a student of 7th semester Electronics & Communication engineering. I am my doing my Minor Project in design of "Currents Mirrors" in VLSI field, in which I am using "Pyxis Schematic" and "Pyxis Layout"(version 10.0) for simulation. I have successfully done the pre layout simulation and I want to do post layout simulation. But I am facing problem to make the layout of any resistor. Because tool is not making the instance of resistor by clicking on resistor and then clicking "Ints" button in "Pyxis Layout"(as we are doing to make instance on MOS). Please help me to makee the layout of any resistor. I am using 0.5 um technology. Show me the step by step method to create the layout of resistor and which layer of material I should select for resistor. I am using 401 KOhms of resistor.

Regards,

Paragh

How to change the component's origin with no changes in Layout Design?

community_admin@mentor.com — Tue, 26 Jun 2012 09:17:54 GMT

I am using PADS Layout. Do you know if it is possible to change the component's origin with no changes in Layout Design, somehow fix the component? Because as I know when the origin of component changes the software automaticaly moves the component in the design according to new origin.. (I have already placed all the components and routed them)

Can anybody help me?