DRC, LVS, Parasitic Extraction - Calibre

Welcome All Content (128) Discussions (124) Documents (4) Set as default tab

Welcome to the DRC, LVS & Parasitic Extraction Forums !

Success in today's IC design and manufacturing industry requires ready access to new ideas and innovative techniques beyond the 4 walls of your company. That's where the IC Layout Verification and Optimization Community can help. This community enables a forum to exchange thoughts and ideas on the challenges and opportunities that come with nanometer-age IC creation. Check back often for new discussions or start one of your own.

Subject		Author
	Re: Virtuoso/Calibre RVE set context 11 hours ago	by gford
	Re: Request for a script that reads in an LVS rules file (SVRF) and outputs TRACE PROPERTY statements for every property on each defined DEVICE? 22 hours ago	by Tricia_Allgyer
	Re: warnings messages during calibreview generation 3 days ago	by karen_chow
	Re: Can Calibre do LVS for a Cadence design with mixed schematic view and CDL netlist view? 4 days ago	by chris_balcom
	Re: question about automatch switch? 1 week ago	by 5973lirm
	Re: Introduce yourself 2 weeks ago	by Mentor_Christine
	Re: 45 degree routing RC extraction 3 weeks ago	by andrewng
	Re: Why "sh: pipo：command not found" appeared in cadence CIW when I chick runDRC after runset set? 3 weeks ago	by chris_balcom
	Re: Polygon to rectangle 3 weeks ago	by tom_donnelly
	Re: How to differentiate edges which are angled at 45 and 135 to x-axis using calibre SVRF elements 1 month ago	by sunilk11

Subject		Author
	calibre.vim : Syntax Highlight for MGC SVRF (Calibre) Standard Verification Rules Format 1 year ago	by Community_Admin
	Utility for creating a cell mapping file 1 year ago	by karen_chow
	HCELL selection methods 1 year ago	by chris_balcom
	Scripts for running batch jobs of Calibre xRC with multiple 1 year ago	by karen_chow