Sometimes I think we are so close to IOD in our team that we forget that some of the functionality that we have sweated to introduce is unknown to our users .
I think most users are familiar with the "FPGA First" design flow starting the FPGA interface definition with HDL (VHDL or Verilog). This is a natural design flow as the HDL files are mandatory in the FPGA implementation process.
What you may not be aware of is that IOD also supports a "PCB First" design flow paradigm. The usage model is that you start in DxDesigner and you create a top level block diagram of your design (this is very handy for multi-FPGA designs). You place blocks for the FPGAs and then you drag nets and busses onto the block to create a connection (interface) to the FPGA.
You then invoke IOD, add a new FPGA device to the project and use the "Import --> PCB Wizard" to select the block that you would like to import the interface definition from. Once this is done you may then generate the top level HDL file to start the FPGA design process with.
Once you have your interface definition you follow the normal FPGA design process to select your FPGA device, assign IO Standards to the signals, assign the signals to pins and drive through the rest of our FPGA - PCB product design flow.
It is not the case the "FPGA First" is better than "PCB First" or that "PCB First" is better than "FPGA First". This is an expression of design style preference and for some designs one design style fits better than another. I will say that if you are working on a feasibility analysis of a product design with multiple FPGAs that the "PCB first" style is a more natural extension of the thought process. I happen to be a graphical processing "thinker" so the PCB First style is more closely aligned with how I think about new product designs. I suspect that if your mind is aligned with "language processing" that the FPGA First style will be a close fit.
If you have any questions or comments on this topic feel free to drop a response!
We prefer PCB First , FPGA late methodology. This save development times. During the period of PCB Layout, FPGA designer are doing thier HDL codings.
I have found we need a mix of both.
Some interfaces are FPGA-first
- Interfaces used on previous FPGA designs where we have VHDL/UCF already
- Interfaces generated by FPGA IP tools (e.g.memory interfaces from the Xilinx MIG)
Other interfaces are PCB first
- New interfaces where VHDL not yet available
A way of merging signal definitions from different sources would be useful.