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13,203 Views 13 Replies Last post: Feb 17, 2012 8:55 AM by cristian.filip RSS
yu.yanfeng EDA JEDI 1,202 posts since
Jul 23, 2008
Currently Being Moderated

Sep 27, 2010 7:10 AM

Running IBIS-AMI Channel Analysis Can't Produce A Realistic Eye.

Hi Steve,

I try to run IBIS-AMI channel analysis on HL 8.1. The problem is that a realistic eye can't generated out. The IBIS-AMI model from LSI and it generated by Sisoft. When  Personnally, I suspect HL8.1's analog channel responce which seems wrong. I have logged a SR #2334590537 on the supportnet and testcase attached.  Please help verify this symptom.

 

If this model be compatible with HL8.1, I hope get a detailed  guide to how to use this model in HL 8.1, especially in step for how to generated a realistic responce for the channel and what need to take cares during running HL 8.1 IBIS-AMI Wizard.

Much thanks

Yanfeng

Steve_McKinney Aficionado 151 posts since
Jul 10, 2008
Currently Being Moderated
Sep 29, 2010 4:45 PM in response to: yu.yanfeng
Re: Running IBIS-AMI Channel Analysis Can't Produce A Realistic Eye.

Hi Yanfeng,

 

The eye diagram that you see is shifted as a result of the clock times produced by the AMI model.  This relates to the CDR behavior within the receiver and we are only displaying what the AMI model is telling us to display.  This is not a limitation of our tool because we are implementing what the AMI specification defines (input data signal is sampled at exactly one half clock period after a clock time) , rather this model isn't behaving appropriately relative to the AMI specification. 

 

-Steve

david.royle Contributor 26 posts since
Jun 23, 2011
Currently Being Moderated
Jul 7, 2011 12:06 AM in response to: yu.yanfeng
Re: Running IBIS-AMI Channel Analysis Can't Produce A Realistic Eye.

Yanfeng, Steve,

 

Greetings,

 

What did you do to fix this?

I am having the same issue modeling Altera GT part at 11.3Gbps. Looking through the IBIS AMI model spec it looks like the sample interval and bit_time are passed from the EDA platform (Hyperlynx) to the shared library (AMI algorithm), not the other way around.

 

Thanks,

Dave

chuck_ferry Lurker 3 posts since
Oct 8, 2008
Currently Being Moderated
Jul 7, 2011 10:29 AM in response to: david.royle
Re: Running IBIS-AMI Channel Analysis Can't Produce A Realistic Eye.

The “clock_times” can be produced by the AMI DLL.  This is the vector that is used to sample the output waveform data.  The details relating to clock times can be found within BIRD112 http://eda.org/pub/ibis/birds/bird112.txt

 

As to your specific issue with this Altera IBIS AMI model Mentor Customer support may be able to help you.

anum.el.27 Contributor 10 posts since
Feb 10, 2012
Currently Being Moderated
Feb 12, 2012 9:46 PM in response to: yu.yanfeng
Re: Running IBIS-AMI Channel Analysis Can't Produce A Realistic Eye.

Hi

 

can anyboby on this discussion tell me what are the requirements for performing IBIS-AMI channel analysis. I want to simulate LVDS signals transmitted from Virtex 5 GTP transceiver to a V5 GTP receiver connected on a backplane through PCI-e. I have IBIS-AMI models for V5 GTP transceiver provided by xilinx but I dont have the s- parameter package models for driver and receiver and also I dont have the model for PCI-e connector. from where can I get my required models? and what model should I use for the channel?

 

Thanks

david.royle Contributor 26 posts since
Jun 23, 2011
Currently Being Moderated
Feb 13, 2012 12:31 PM in response to: anum.el.27
Re: Running IBIS-AMI Channel Analysis Can't Produce A Realistic Eye.

Anum,

Are you sure your V5 GTP interface is not CML?

 

The Xilinx Signal Integrity Simulation Kit includes package parasitic file in Touchstone format (.s4p).

 

You get s-parameter data from the connector vendor, they probably have it if it is intended for GHz rate signals. They are often not posted on www, you may have to work with a sales rep to get the data.

 

Hyperlynx creates the models of the board's traces and vias from your board files. You will run PCB translator to convert you board files to Boardsim. You will set up libraries to include your Xilinx parts and connector. You will specify the stackup data under Boardsim. If your simulation involves two boards inserted into a motherboard then you will want to run PCB translator on each (and stackup data for each) and set up a multiboard simulation.

Next you will have to select, from within the multiboard sim, your desired signal and export it to a free form schematic (LineSim) so that you can insert your Xilinx package parasitics block between the FPGA and the board traces. There are a few things you should do to the LineSim schematic and IBIS model at this point before you simulate that I will not go into here. Ultimately you will set up the IBIS-AMI model parameters from within LineSim and run the simulation.

 

Hope this gets you started.

Dave

anum.el.27 Contributor 10 posts since
Feb 10, 2012
Currently Being Moderated
Feb 16, 2012 9:39 PM in response to: david.royle
Re: Running IBIS-AMI Channel Analysis Can't Produce A Realistic Eye.

Dave,

 

thanks for your guidance.

the Virtex 5 GTP interface is CML.

 

I have downloaded the xilinx signal integrity simulation kit (ug351_v5_rio_sis_kit_2_0_beta_eldo.zip) from XILINX and mentor rocketIO simulation kit (HL_Xilinx_Kit_V_3_7_zip~) from mentor graphics for performing simulations of V5 GTP Transceivers but I am facing problems in integrating them. on executing the install file (Install_HypSisKit.exe), it asks for the xilinx kit, I am providing the path for the kit but it always says xilinx SISKIT not found. I guess some required folders are missing in the xilinx SISKIT due to which it is not getting integrated with the mentor rocketIO kit. what should I do now because mentor rocketIO kit won't work properly unless xilinx SISkit gets found.

 

plz help me in sorting out the actual problem.

 

Thanks again!

cristian.filip Aficionado 100 posts since
Mar 2, 2009
Currently Being Moderated
Feb 17, 2012 8:55 AM in response to: anum.el.27
Re: Running IBIS-AMI Channel Analysis Can't Produce A Realistic Eye.

I haven’t work with those kits recently, but from what I remember HL_Xilinx_Kit_V_3_7_zip is an old version (for HyperLynx 7.5) and I believe that is not for V5. I would suggest you reading the ug512 document that you can find in the ./docs sub-directory of the ug351_v5_rio_sis_kit_2_0_beta_eldo.zip. It contains detailed instructions about how to use this kit.

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