I am performing DDRx Batch Simulation for Octeon processor and DDR3-1333 interface. The timing models required for DDR3 are fine, but I need to make a timing model for the controller as per my controller specs....
I referred to App note 10706 (Creating Hyperlynx DDRx Memory controller Timing Model), but still have doubts in some parameters as some details given in controller datasheet matches few paramters given in each of the 3 examples given in the application note. Also there is no timing diagram given in the datasheet. Can anyone help me with this thing?
I am attaching the controller parameters given in the datasheet.
Thanks in advance.
Mentor Graphics customer support can help you work it out. You should open a service request on supportnet.mentor.com.
I think that all the necessary information is in the table that you showed, but it is presented slightly differently than the parameters used in the controller timing model.
Thank you for your response. I had already raised an SR for that, but they said that they can't help us in this regard. Anything tool related, they would help us, but not in deriving the required parameters.
OK. I understand. This what I suggest. Use the application note and make your best effort to create the controller timing model. Then send it to me firstname.lastname@example.org and I can check it. I suggest that you draw the timing diagram to represent the timing specification in the data sheet. This picture will help you correlate with the timing diagrams in the application note. Use the timing model wizard in the HyperLynx installation directory to get the data in the right format and verify that the timing diagrams from the model make sense.