I am running HDL Designer for Windows 7 64 bit. Every time I try to create a block using with combined VHDL coding, the default template never shows up when the coding window opens and none of the changes I make to the block ever save. Does anyone have any idea what the problem might be?
Are you using the latest 2010.3 release? If not I would suggest you try that one. If designpad opens navigate to the Document->Language menu and make sure VHDLXXXX is selected. Next click on the View menu and check that the Language Templates is ticked. On the bottom left of your editing screen you should see the templates.
Regarding the saving issue, can you provide some more info, do you get an error message, is the file/folder you are using read-only?
I would also suggest you contact your Mentor/Distributer office to see if one of the engineers can do a webex/gotomeeting with you. This normally fixes issues quite quickly.
Yes, I am using the 2010.3 release.
I tried opening DesignPad and following the steps you provided, but it has had no effect on the project file.
The project consists of a top-level component, inside of which is a block diagram. I am trying to set up one of the blocks in that diagram to write out Combined VHDL coding. The problem is, the default starting template that is supposed to appear when the code writing window opens does not appear. From what I understand, this means the program can't find the template I need.
This is the top-level component:
This is the block diagram within the component:
The left hand block is the one I am attempting to write VHDL code to.
These are the settings I am giving the block:
This is what I should be seeing when the code window opens:
This is what I am actually seeing:
I hope this clarifies things.