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109,892 Views 16 Replies Last post: Jan 20, 2014 1:58 AM by soumya.artabandhu RSS
anum.el.27 Contributor 10 posts since
Feb 10, 2012
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Feb 12, 2012 8:24 AM

DDRx simulation in hyperlynx 8.1

Hi all

 

Is it possible to perform DDR2 timing analysis in linesim by simulating two or more DDR signals simultaneously for e.g. simulating data and strobe or clock and address at a time.

 

Thanks

weston_beal Aficionado 165 posts since
Sep 4, 2008
Currently Being Moderated
Feb 13, 2012 3:44 PM in response to: anum.el.27
Re: DDRx simulation in hyperlynx 8.1

Yes, you can do this. You need to use per-pin stimulus to get the correct time offset between the two signals' stimulus and bit patterns. After than you can measure the setup and hold times between the two signals at the many edges. I recommend using an oscillator bit pattern for the strobe (or clock) and PRBS for the data (or address/command/control) signal.

cristian.filip Aficionado 100 posts since
Mar 2, 2009
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Feb 17, 2012 8:25 AM in response to: anum.el.27
Re: DDRx simulation in hyperlynx 8.1

The models assignment for DDRx Wizard is no different than the one for interactive or batch mode simulation, so yes in case if your IBIS contains models for more components you have to choose the right component for your design. To do that, go to Models -> Assign Models/Values by Reference Designator (.REF File) menu. Then on the Design’s part list section select the memory IC’s that you want to assign models to, check .IBIS/.EBD under the Library section, choose the proper IBIS model from the dropdown list and finally pick the right component from the Components/models dropdown list. Last step, click on the Assign Model button and save the .REF file. DDRx will use this .REF file and will recognize the model assignment that you made here.

weston_beal Aficionado 165 posts since
Sep 4, 2008
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Feb 17, 2012 10:15 AM in response to: cristian.filip
Re: DDRx simulation in hyperlynx 8.1

That's a good description of the procedure by Cristian. One additional thing that you need to know is that interactive pin model assignment done in the Assign Models window override the REF file model assignments. Make sure that when you assign part models through the REF file (the correct method in this case) that you remove any pin level model assignments on that part.

cristian.filip Aficionado 100 posts since
Mar 2, 2009
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Feb 21, 2012 6:40 AM in response to: anum.el.27
Re: DDRx simulation in hyperlynx 8.1

If you have assigned the models using .REF file, there is no need for per pin assignment. From your description it is really difficult to understand what’s wrong with your setup, but you can try simulating in interactive mode. Assuming that the models and their assignment are correct you should be able to properly simulate.

 

To debug you can do the following:

 

1.       1. Disable crosstalk, select a DDRx net and go under Models -> Assign Models/Values by Net. All the drivers, receivers and terminations are listed there and the models should be properly assigned. If not check either your .REF file or IBIS models.

2.       2. Set the proper buffer settings (Input, Output, Output Inverted) and simulate. If everything was ok at 1. you should be able to properly simulate.

3.      3.  Assuming that 1. and 2. went well DDRx should properly work.

4.       4. While in DDRx wizard you can double check the models assignment (IBIS Models step -> click on Assign Component Models).

 

Hope this helps.

cristian.filip Aficionado 100 posts since
Mar 2, 2009
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Feb 21, 2012 7:19 AM in response to: cristian.filip
Re: DDRx simulation in hyperlynx 8.1

I guess that the issue is your memory controller model (Xilinx V5). Did you customized it manually or using ISE tool? If you simply downloaded it from Xilinx website this model is not ready for simulation.

cristian.filip Aficionado 100 posts since
Mar 2, 2009
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Feb 22, 2012 7:12 AM in response to: anum.el.27
Re: DDRx simulation in hyperlynx 8.1

The IBIS model provided by Xilinx is not targeting a specific device-package combination, but it is just a collection of models for various available I/Os within the V5 family. Consequently the [Pin] section of the model doesn’t reflect a real pin out with proper signal name. This is how this section looks like:

 

|************************************************************************

[Pin]  signal_name          model_name

198   LVCMJED18_F_4_TB_33       LVCMJED18_F_4_TB_33

199   LVCMJED18_F_6_LR_25       LVCMJED18_F_6_LR_25

200   LVCMJED18_F_6_LR_33       LVCMJED18_F_6_LR_33

201   LVCMJED18_F_6_TB_25       LVCMJED18_F_6_TB_25

 

However after customization your model should match your devices pin out as per your schematic and PCB layout symbols. The customized model will look like:

 

|************************************************************************

[Pin]  signal_name          model_name

L19      mcb1_dram_dm(0)      SSTL15_OT50_LR_33

M20     mcb1_dram_dm(1)      SSTL15_OT50_LR_33

N20      mcb1_dram_dq(0)      SSTL15_OT50_LR_33

N22      mcb1_dram_dq(1)      SSTL15_OT50_LR_33

K22      mcb1_dram_dq(7)      SSTL15_OT50_LR_33

P21      mcb1_dram_dq(8)      SSTL15_OT50_LR_33

 

Another important think is the package modeling. If you use the information contained within the [Package] section that will assign same package parasitic (R,L,C) for every pin (an average for your specific package). That will affect your timing. In order to properly model the package delays (skew) you will need different R,L,C values for each pin. Xilinx provides the package models separately as “*_ibis.pkg” files. You have to add this package model into your IBIS model using [Define Package Model] keyword. Be aware that although this type of package model includes coupling between various pins, HyperLynx will ignore it, but will simulate using the proper delays. The easiest way to customize the FPGA models is by using vendor specific tools (Xilinx ISE in this case), so you don’t have to know too much about the IBIS syntax. If you want to do it manually you can search on Xilinx website and you will find some good documents explaining in detail this process. You might want also to have a look at various appnotes from Mentor as well.

sandeep.bansal Lurker 3 posts since
Oct 29, 2012
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Oct 30, 2012 3:28 AM in response to: cristian.filip
Re: DDRx simulation in hyperlynx 8.1

Hi,

 

How can i export more than one nets from 8.hyp file to sch? or i need to draw schematic only.

hans.klos Lurker 1 posts since
Aug 14, 2009
Currently Being Moderated
Dec 21, 2012 1:44 AM in response to: cristian.filip
Re: DDRx simulation in hyperlynx 8.1

If you want to do a timing analysis for an FPGA, you need to do the following steps:

 

1) Edit your ibis model of the FPGA, to create the model selector section(s) (example below of a Kintex-7):

[Model Selector] DDR3_ADDR

SSTL15_S_HP Output

SSTL15_F_HP Output

|

[Model Selector] DDR3_CTRL

SSTL15_S_HP Output

SSTL15_F_HP Output

|

[Model Selector] DDR3_CLK

SSTL15_S_HP Output

SSTL15_F_HP Output

|

[Model Selector] DDR3_DQ

SSTL15_S_HP Output

SSTL15_F_HP Output

SSTL15_DCI_HP_I Input

SSTL15_DCI_HP_IN40_I Input

SSTL15_DCI_HP_IN60_I Input

SSTL15_DCI_S_HP_O Output

SSTL15_DCI_F_HP_O Output

|

[Model Selector] DDR3_DQS

SSTL15_S_HP Output

SSTL15_F_HP Output

SSTL15_DCI_HP_I Input

SSTL15_DCI_HP_IN40_I Input

SSTL15_DCI_HP_IN60_I Input

SSTL15_DCI_S_HP_O Output

SSTL15_DCI_F_HP_O Output

|

[Model Selector] DDR3_DM

SSTL15_S_HP Output

SSTL15_F_HP Output

SSTL15_DCI_S_HP_O Output

SSTL15_DCI_F_HP_O Output

 

You then need to set the e.g. DDR3_DQS model for each DQS pin (pin section) and do the same for the other groups)

 

2) Create a timing model for your FPGA controller

This is a more difficult  task because it's difficult to obtain the timing information to create a timing controller model in Hyperlynx.

For a processor it's more easy to create your own timing model, because most vvendors supply all the information in their datasheet.

For the memory, you don't need to create a timing model, because you can use the supplied jedec models, included in the Hyperlynx package.

3) If you want to simulatie die-die timing for your DDRx interface, you'll need to set the Timing location statement in your ibis model as well:

[Component] kintex-7-sintecs

Timing_location Die

 

Now you can go through the Hyperlynx DDRx wizard and setup your simulation.

 

I hope this helps.

Hans Klos

dave.cowl Contributor 8 posts since
Nov 28, 2011
Currently Being Moderated
Jul 15, 2013 4:18 PM in response to: hans.klos
Re: DDRx simulation in hyperlynx 8.1

Not sure if anyone is looking at this thread anymore.

 

I am having issues with the simulation and I suspect that the IBIS file is the source.

 

Looking at the difference between the models for SSTL15_DCI_HP_IN40_I and SSTL15_DCI_HP_IN50_I reveals very little difference, so I am wondering if the Xilinx models even really support variation in the termination impedance.

 

I am thinking that if my 40 ohm system is seeing 50 ohms termination at the Xilinx, it is likely the cause of my ringing issues on the line.

 

Does anyone have any insight into simulating Kintex 7 with 40 ohm DDR3 traces?

 

Cheers! Dave.

dave.cowl Contributor 8 posts since
Nov 28, 2011
Currently Being Moderated
Jul 15, 2013 4:29 PM in response to: dave.cowl
Re: DDRx simulation in hyperlynx 8.1

I exported one of the traces to a free form schematic.

 

If I replace the Xilinx part with a 40 ohm resistor to ground I get no ringing to speak of, so I think that the Xilinx model is not presenting a suitable 40 ohm load at the receiver end.

 

If anyone has any suggestions as to how to fix this please let me know!

 

Cheers!

dave.cowl Contributor 8 posts since
Nov 28, 2011
Currently Being Moderated
Jul 15, 2013 4:48 PM in response to: dave.cowl
Re: DDRx simulation in hyperlynx 8.1

Further to this...

 

Looking at the waveform at the die appears to be clean also.

 

So my new assessment is that the package characteristics mean that while it is clean at the die, the signal at the package pin is far enough away from the die connection to have a bad waveform that is not representative of the received signal.

 

So now if I can only get the DDRx wizard to see it that way...

 

Cheers! Dave.

soumya.artabandhu Lurker 1 posts since
Jan 19, 2014
Currently Being Moderated
Jan 20, 2014 1:58 AM in response to: hans.klos
Re: DDRx simulation in hyperlynx 8.1

Sir can you please give some idea to creating timing model for FPGA ?

In FPGA data sheet the exact term for the various time is not mentioned.

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