I have an empty schematic cell that brings to errors during verification. In the mean time I don't want to use "LVS SPICE CULL PRIMITIVE SUBCIRCUITS" command. How and what funtionality can I use to make these cells to be treated as non-primitive cells without using LVS SPICE CULL PRIMITIVE SUBCIRCUITS command.
This can be added to the rule file to filter away certain empty subcircuits from the source by name:
LVS FILTER mysubname OPEN SOURCE
Thanks for your response Chris.
Actually I don't want to filter them out. Just imagine that I have empty subcircuits in a schematic netlists which have appropriate layouts. And I want to gave a tool to not see them as an empty subcircuits.
I'm not aware of a way to treat an empty subckt as non-primitive. Maybe someone else reading this has an idea?