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22,090 Views 1 Reply Last post: Jun 8, 2012 11:11 AM by Guy RSS
rohini.patil Lurker 1 posts since
May 17, 2012
Currently Being Moderated

Jun 8, 2012 12:26 AM

Difficulties in mapping component

Hello All,

I have added a VHDL module file in one of the user made libraries in my project.

But I am getting an error of unbound component in the project when i try to instantiate it as a component in one of my wrapper.

Does anyone knows how to connect the vhdl module as a component in the project?

Guy jedi 289 posts since
Apr 1, 2008
Currently Being Moderated
Jun 8, 2012 11:11 AM in response to: rohini.patil
Re: Difficulties in mapping component

What tool are you running?

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