i am getting following error in LVS report
5 ** missing net ** VDD
--------------------------------------------------------------------------------------------------------------
6 ** missing net ** VSS
**************************************************************************************************************
INCORRECT PORTS
DISC# LAYOUT NAME SOURCE NAME
**************************************************************************************************************
7 ** missing port ** VDD on net: VDD
8 ** missing port ** VSS on net: VSS
and it is showing in detailed report LVS REPORT OPTION
--- Devices on source net VSS ---
(cell ports) (cell ports)
VDD_PLL: VDD_PLL VDD_PLL: VDD_PLL
VDDA_PLL: VDDA_PLL VDDA_PLL: VDDA_PLL
VDD: VDD VDD: VDD
VDD_MDDI: VDD_MDDI VDD_MDDI: VDD_MDDI
VDDA_MDDI: VDDA_MDDI VDDA_MDDI: VDDA_MDDI
VCCQ: VCCQ VCCQ: VCCQ
vddz: VDDZ vddz: VDDZ
vddana: VDDANA vddana: VDDANA
VSS: VSS VSS: VSS
VSSA_MDDI: VSSA_MDDI VSSA_MDDI: VSSA_MDDI
VSS_PLL: VSS_PLL VSS_PLL: VSS_PLL
VSSA_PLL: VSSA_PLL VSSA_PLL: VSSA_PLL
VSS_MDDI: VSS_MDDI VSS_MDDI: VSS_MDDI
vccio_2_: vccio_2_ vccio_2_: VCCIO_2_
gpio_57: gpio_57 gpio_57: gpio_57
vpp6: vpp6 vpp6: vpp6
mddi_d0_n: mddi_d0_n mddi_d0_n: mddi_d0_n
.
.
.
.
adq0_2_8m_ad7_2_16m: adq0_2_8m_ad7_2_16m adq0_2_8m_ad7_2_16m: adq0_2_8m_ad7_2_16m
adq1_2_8m_ad6_2_16m: adq1_2_8m_ad6_2_16m adq1_2_8m_ad6_2_16m: adq1_2_8m_ad6_2_16m
adq1_1_8m_ad6_1_16m: adq1_1_8m_ad6_1_16m adq1_1_8m_ad6_1_16m: adq1_1_8m_ad6_1_16m
** missing net ** VDD: VDD
** missing net ** VSS: VSS
also showimg
Source Names That Appear On More Than One Object:
Ports: VDD VSS
Nets: VDD VSS
can any one please explain why the tool showing 2 VDD & 2 VSS in source net list
Hi Suresh,
Is it possible that there were two different ground names in the source, and that *.EQUIV was used to bring them together as VSS ? That doesn't work the same way as *.CONNECT or *.JOIN which actually join together nets of different names.
Here are links to a few TechNotes that describe this problem and solution in more detail:
http://supportnet.mentor.com/reference/technotes/public/technote.cfm?tn=MG76485
http://supportnet.mentor.com/reference/technotes/public/technote.cfm?tn=MG44056
Hi Suresh,
I think, It should be probably because of pwr/gnd net openings. Check whether you have defined toplevel port name for your pwr/gnd pins
in the layout. If not, use the 'LAYOUT TEXT' option to define the top-level pg pins. It will help to isolate the pwr/gnd nets open. And make sure
your lvs extraction report is clean for this case.
- Karthik