GREG D. YOUNG

154 Brentwood Drive

Georgetown, Texas  78628

(512) 868-8533                                                                                             greg.young@capitol-best.org

SUMMARY

Highly accomplished Test Engineer with extensive experience in Design for Test (DFT) and Embedded Test from IC to system level.  Highly effective leader and technologist with commercial (semiconductor) and military design background.  Experienced with Synopys, Cadence and mentor Graphics test automation tools; Virage SMS memory BIST/repair.  Independent, multi-tasking worker with strong reputation as a mentor.  Direct experience with:

PROFESSIONAL EXPERIENCE

FREESCALE SEMICONDUCTOR, INC., Austin, Texas                                         2004-2009

Member of Technical Staff / DFT Engineer

Design-for-test methodology, architecture and execution for multiple ARM-based core designs. Concentration on low-power DFT and test pattern reuse.

• Trained and mentored new DFT engineers and co-op students.
• Led DFT/TE Subprocess Development Team.
• Completed test architecture, implementation, and test pattern development for multiple cores.
• Created test automation flows for Synopsys/Cadence synthesis with Mentor ATPG and Virage memory BIST.
• Automated custom memory ATPG model creation saving weeks of manual effort per model.
• Created and implemented low-power DFT architecture for advanced core design.
• Developed automation flow/scripts/tools (shell script, TCL) for insertion of shared functional scan wrapper and creation of modular test compression RTL.
• Pioneered ram sequential ATPG and low-power structure testing to improve ATPG test coverage on cores by 5%.

MOTOROLA, INC., Austin, Texas                                                                            2000-2004

Design/Test Engineer

DFT/Test methodology and implementation for complex embedded core platforms. Support multi-core SoC integration via world-wide design centers.

• Developed DFT guidelines and standards for reusable core designs.
• Created standard DFT development process, documentation process and documentation templates streamlining operations and resolving inaccurate data transfer between organizations.
• Contributed to IEEE Standard 1500 (Core Test Architecture) working group.
• Created tool validation process to verify tool change requests and new releases.

RAYTHEON SYSTEMS COMPANY, Dallas, Texas                                                            1998-2000

Member Group Technical Staff / Testability Engineer

Developed DFT processes and tools for Application Specific Integrated Circuit (ASIC) designs and Circuit Card Assemblies (CCA). Defined test requirements, embedded test architecture and implemented embedded test structures. Defined embedded test software (built-in test) architectures for CCA and subsystems. 

• Completed embedded test architecture definition and analysis per MIL-STD-2165 for ASIC, circuit card assemblies (CCA), and subsystems for F-16 and F-22 avionics.

• Created and deployed company-wide ASIC DFT development process; established vendor partnerships regarding Memory BIST and Logic BIST research to meet company needs.
• Conducted multi-site ASIC DFT video conference training seminar.

TEXAS INSTRUMENTS, INC., Dallas, Texas                                                                      1985-1998

Member Group Technical Staff / Testability Engineer

Developed and implemented common test solutions/standards for ASICs, CCAs, and subsystems.

• Completed test architecture and implementation achieving customer requirements for multiple processors, ASICs (200K to 2M+), FPGAs, multichip modules, CCAs and subsystems.
• Contributed to IEEE Standard 1149.5 (Module Test & Maintenance Bus) working group.
• Developed/implemented test methods for 1^st multi-chip module (MCM) stacked die memory and stacked-MCM high-performance processor for the Defense Advanced Research Projects Agency (DARPA).
• Standardized ASIC boundary scan baseline architecture, created VHDL reuse library and automated VHDL testbench creation for verifying compliance.
• Designed, wrote and verified Built-In Test software for TI GPS system.
• Recipient of TI’s Technical Award for Excellence & Advance Systems Division Quality Award.
• Achieved Top Secret government clearance.

AFFILIATIONS

IEEE                                                                                                                           1982–2009

Member, IEEE Test Technology Technical Committee.

BEST ROBOTICS, INC. (http://www.bestinc.org)                                                     2003–2009

Member, Board of Directors. Non-profit organization.

Boosting Engineering Science and Technology, a national high school robotics program.

• Led development of programmable control system; procurement, order, fulfillment and training.
• Perform strategic planning, public awareness, control system development, teacher & volunteer training development.

CAPITOL BEST, INC. (http://www.capitol-best.org)                                                 2001–2009

President, Chairman of the Board. Non-profit organization

Organize and direct annual regional robotics contest. Austin hub of BEST Robotics, Inc.

Grant writing, fundraising, volunteer recruitment/management, university partnerships, website development/management, parts ordering/kitting, field construction, program publicity, event management duties, and much more.

EDUCATION

Bachelor of Science Electrical Engineering.

Southern Methodist University, Dallas, Texas.