• How to get the pin order wanted in my extraction netlist from Calibre xRC?

      How to get the pin order wanted in my extraction netlist from Calibre xRC?    
    last modified by karen_chow
  • Calibre - Check to highlight if a Gate does not connect to P-diff

    I would like a simple check to highlight nets which connect only to gate(s) (n and/or p) and only ntype S/D diffusion. I am not sure which way to address it 
    last modified by mattb73
  • xdx designer

    How to configure the symbols in the xDX Designer. Please tell me anyone answer.
    created by rajivm
  • How to run calibre -drc in background

    Hi,     I would like to turn off the ability of the drc run to show the transcript off the run during its run.   Is there a switch for that?     Thanks, Michael
    last modified by michael.shuster
  • [Questa] $MODEL_TECH -> where is defined? where should point?

    Hi All,   As for the $MODEL_TECH variable, where is it defined? Where should point to?   Thank you!
    last modified by ldm.eth
  • glbl + vcom/vopt/vsim libraries -> when used?

    Hi All,   1) What is the glbl library? What does it include and why needed?   2) What libraries should be loaded with the vsim command? Some libraries should be loaded/compiled with vcom, some of them with...
    created by ldm.eth
  • Calibre LVS: How to compare the intrinsic diode (parasitic diode btw nwell & psub) area in LVS?

    Hi I'm trying to extract the intrinsic Nwell- Psub diode area for accurate modelling. How can I make Calibre LVS to recognise the intrinsic diodes and compare the diode area against a schematic model?   Thanks.
    last modified by kkmovva
  • DRC SVRF codes for checking the coordinates

    Good day to all, I would like to ask if there are SVRF code for DRC that will help to check the coordinate of the origin of a layer. I need to check a certain layer coordinates if its a multiple of a certain number li...
    last modified by apanonue
  • Installation QuestaSim 10.6c

    How to find the installation files of QuestaSim 10.6c window version ?
    last modified by joniengr081
  • Debugging using Step Into and Step Over

    The blue arrow (as shown in the attachment) points somewhere at the end of the testbench after the simulation is complete and yellow line on the wave window also pointing at the end of the time which we set in simulat...
    created by joniengr081
  • Font change in Questa - HDL files

    Is there any way to change the font size (zoom-in and zoom-out) the HDL files which are opened in Questa ? I know there is a possibility to dock and un-dock but still I am not able to change the syntax font size. Is i...
    created by joniengr081
  • Empty layer define in Calibre DRC/LVS

    Hi, I want to define an empty layer. Is it possible in Calibre LVS/DRC? (The reason is this layer is not present in current version of PDK, but it will be added later in the stable PDK release). Currently, we don't ...
    last modified by venkateshwarlu
  • Calibre menu configuration in Cadence

    Hi everyone,   Could you help me out by pointing to the appropriate documentation or by hints how could I configure the Calibre menu in Cadence? I was consulting with Calibre ® Interactive TM and Calibre &...
    last modified by horror-vacui
  • Questa GCC Packages

    Hi, I am wondering about Questa GCC package "questa_sim-gcc-4.5.0". How important is this package after Questa installation ? What does it include ?
    last modified by joniengr081
  • Adding compiled libraries in Questa simulation

    Hello, I have downloaded complied smartfusion2 libraries. I am wondering how and where to add them in Questa simulation. Is there any example ?
    last modified by joniengr081
  • VSS and VDD08  short in the source netlist

    dear all,   I encounter a LVS issue.  My top source netlist has 34 ports , but after merging nets or filtering instances in source , it show the following  Error   Error: Power Shorted to ground...
    last modified by gzh9255
  • How to get Calibre DRC to write out a GDS file

    I have a SKILL and DIVA DRC deck combination that automatically deletes DRC dirty fill pattern for metal only revisions.  Unfortunately it no longer works after IC6.1.5, so I am trying to "update" the flow to use...
    last modified by yetanothermike
  • Cannot recognize diode device in PERC LDL CD/P2P ?

    I followed the example of PERC LDL CD/P2P and applied to my design. The example is to check current density and point-2-point resistance from IO pad to Power and Gnd for the ESD-1st. In my design, I use the n type dio...
    last modified by hungtruong
  • Question abot LVS: "Error:    Components with non-identical signal pins."

    I have resistor device with 2 terminal + 1 inherit (sub!) DEVICE R (rhigh) Rhigh_edge GP_connect(POS) GP_connect(NEG) bulk(SUB) <edgeLayer_Rhigh>   In the test I put 3 resistors in parallel.   In l...
    last modified by medan
  • DESIGNrev: remove all polygons and references underneath a rectangular area

    Hello All,   I'm hoping this is the correct place to post this question.  In DESGINrev, is there a way of efficiently removing all shapes (polygons, references, paths, etc.) that lie beneath a rectangular a...
    last modified by papa_g