• How to get Calibre DRC to write out a GDS file

    I have a SKILL and DIVA DRC deck combination that automatically deletes DRC dirty fill pattern for metal only revisions.  Unfortunately it no longer works after IC6.1.5, so I am trying to "update" the flow to use...
    yetanothermike
    last modified by yetanothermike
  • Cannot recognize diode device in PERC LDL CD/P2P ?

    I followed the example of PERC LDL CD/P2P and applied to my design. The example is to check current density and point-2-point resistance from IO pad to Power and Gnd for the ESD-1st. In my design, I use the n type dio...
    hungtruong
    last modified by hungtruong
  • Question abot LVS: "Error:    Components with non-identical signal pins."

    I have resistor device with 2 terminal + 1 inherit (sub!) DEVICE R (rhigh) Rhigh_edge GP_connect(POS) GP_connect(NEG) bulk(SUB) <edgeLayer_Rhigh>   In the test I put 3 resistors in parallel.   In l...
    medan
    last modified by medan
  • DESIGNrev: remove all polygons and references underneath a rectangular area

    Hello All,   I'm hoping this is the correct place to post this question.  In DESGINrev, is there a way of efficiently removing all shapes (polygons, references, paths, etc.) that lie beneath a rectangular a...
    papa_g
    last modified by papa_g
  • Is there a way to implement the "die to die results compare" feature as a macro in "TERADYNE Examinator PRO+ tool" ?

    "Compare files Analysis" option generates a report based on the Mean Shift and StdDev shift. In case of mismatch, users need a manual handling of the 2 stdfs to identify the failed X,Y positions. This task is time co...
    j.j
    created by j.j
  • Mirror a gds when merging gds files

    I am using the following command to merge gds files:   calibredrv -a layout filemerge -in filename1 -in filename2 -out output.gds -topcell top   But when merging them, I need to mirror filename2 by Y axis,...
    zysteven
    last modified by zysteven
  • Calibre LVS is not recognizing port names with only numbers

    Hi, I am trying to place a port name with only numerical. Calibre LVS is giving a warning and ignoring the port number. Is there any way i can use port name only numbers that LVS can recognise?     Tha...
    venkateshwarlu
    last modified by venkateshwarlu
  • How to ADD/DEL Connector or Splice in IXHarnessBridgeProcessor

    How to ADD/DEL Connector or Splice in IXHarnessBridgeProcessor
  • Can I do scripting in Pyxis Layout, if so how?

    Hi, I use Pyxis Layout, mainly for mask designing. I normally draw my features but I am looking for writing script and compile to draw features type thing. Is it possible with Pyxis Layout?
    naeem
    last modified by naeem
  • Script error when trying to generate PowerPoint(2016) report

    Generate a report to the PowerPoint 2016 with "Merge files", and then get an script error.
    j.j
    last modified by j.j
  • output spectrum and  PSD curve for OTA-C filter

    How can I get the output power spectrum and PSD curve in ezwave for a OTA-C circuit? i am using Eldo by simulating the SPICE code of the circuit. Suppose, I want to get the the above for a OTA-C linear filter.In tha...
  • Stability analysis of circuits with active devices  in Eldo

    In  Eldo-RF manual, I found "local stability analysis" using .SSt STABIL for a oscillating circuit based on npn transistors along with R L and C. But I am trying to use it for my circuit that is made up of OTA a...
  • Calibre LVS issue with "TRACE PROPERTY" for a device name "step"

    Hi,   I have issues while running Calibre LVS with unselecting "Trace property" in the Calibre Interactive.(Without unselecting any trace properties of any device ). (Intention is to unselect some trace properti...
    venkateshwarlu
    last modified by venkateshwarlu
  • Calibre PEX violations

    Hi,   We have recently upgraded to Calibre release "v2013.2_18.13" and started getting the following errors which were not there before.   WARNING:  Hcells "nmos_rf_25*" and "nmos_rf_25" are of diffe...
    mugofgold
    last modified by mugofgold
  • test

    test
    evaeva
    created by evaeva
  • Mentor launches unique, end-to-end Xpedition High-Density Advanced Packaging flow

    It's here! Mentor has launched the Xpedition® High-Density Advanced Packaging (HDAP) flow; the industry’s first comprehensive solution for the design and verification of today’s leading-edge IC packag...
    Ryan_Kasnick
    created by Ryan_Kasnick
  • chris_balcom

    hi sir, which layer is used for deep n well and deep p well in pyxis layout? please help me its urgent as the license of my software will be expired on 17th may 2017. with regards mayank
    vlsi.mayank
    last modified by vlsi.mayank
  • LVS, PEX, PEX_RUN environment variable issue

    I am trying to run a simulation on an extracted view of my APR design. The design passes LVS when I set PEX_RUN = FALSE. However, when I set PEX_RUN = TRUE, LVS fails (PEX does complete and create a calibre view). Bec...
    bey
    last modified by bey
  • Change Calibre View Setup dialog options when running Calibre xRC in the Cadence environment

    Here's a fairly common question on Calibre Integration to the Cadence environment. Calibre xRC's integration to the Cadence tools provides back-annotation of parasitic results for use when simulating with ADE by crea...
    James
    last modified by James
  • DESIGNrev scripts to share

    Hi DESIGNrev users,   My colleague Saunder has been looking into several ideas for Tcl scripts that run in DESIGNrev. We’re wondering if any of the following topics would be of interest to folks here in the...
    chris_balcom
    last modified by chris_balcom