• when iam opening the created wlf file iam getting below message

    assertions]% Reading pref.tcl WLF file vsim.wlf contains no context information.   Hi,   When i am simulating below code iam getting the message above and waveform is not getting opened. It would be real...
    bharath_vlsi
    created by bharath_vlsi
  • X,Y coordinates of a Cell in GDS

    All,   I have a GDS II open in Calibre DesignRev.  Now I want to get the x,y coordinates of a particular cell in a die. Also, Is it possible to get x,y coordinates of all the cells or particular type (like ...
    makhtar
    last modified by makhtar
  • how to control the drill size for different pin size

    I am looking for the correct way to check if the drill size is not too small/ big for the pins of TH devices.     I was using the "Small Hole for Rect Pin" / "Small Hole for Round Pin" / "Small Hole fo...
    amos.kolath
    last modified by amos.kolath
  • how to use coupled inductor in design architech-ic

    Hi, I'm robby, I want to ask question for coupled inductor. How to use coupled indcutor in design architech-ic?, because if I run simulation eldo in schematic, I get error "OBJECT "K1" :Undecleared inductor:L2. If I ...
    robbyku13
    last modified by robbyku13
  • TVF functon that print polygon by polygon extents

    Hello all,   I'm trying to write TVF function that will print every polygon extents of derived layer.   I found that I can print only total layer extents with the following command   tvf::GET_LAYER_...
    roman
    last modified by roman
  • Internal Error occurred while generating wdb file.

    Hi, Please find the snapshot of the error while simulating Inverter Test Circuit using Eldo. This error occurs everytime even after reapeted Installation of Pyxis and AMS Sofanks tware. Kindly, Solve the pr...
    k.kumar
    last modified by k.kumar
  • LVS mismatch with extra empty device in source netlist

    In the LVS report, I found there were missing instances layout. After checking the source netlist, I found those missing instances were empty subckt in my cdl netlist. Meanwhile, layout cells with same cell name were ...
    qing.fan
    last modified by qing.fan
  • Adding text string from a file to a layout

    Hi,   I was referring to following link which explains how to add text strings from a file to a lyout:   https://supportnet.mentor.com/portal?do=reference.technote&id=MG242030&lang=en&prod=C110...
    vikky01
    last modified by vikky01
  • Pin order in common sub-circuits

    Hi,   A funny issue we have here with Calibre LVS setup. A toplevel LVS passes with my run.   However, another layout engineer runs the same toplevel LVS and his fails. It seems to be with std cell pin ord...
    kdoherty
    created by kdoherty
  • SPEF file comparison for Calibre xRC and StarRC

    Hello, I run the extraction for my project using xRC and StarRC and the extracted file is in SPEF format. Then I compare the SPEF file using myBingo tool to find pin to pin resistance. The problem is the SPEF files ar...
    Farhan.Rasheed
    created by Farhan.Rasheed
  • Trivial Ports Number different between reports

    Hi,   I am trying to find out all the trivial ports in my layout. If i look at the lvs report and grep the key word "layout trivial ports"   it looks like :     5 layout trivial ports were ...
    vikky01
    last modified by vikky01
  • Mentor graphics interface to Synopsys

    Hai, I want to ask about mentor graphics interface to synopsys. how can mixed two project or layout (1 using mentor Icstation and 1 using synopsys) ?.   thanks,
    robbyku13
    last modified by robbyku13
  • calibre drc for one rules of rules_file?

    Hi,   Is it possible to run calibre drc for one/few rules from a full rules_file? Intention is to check particular layer for DRC and save runtime.   Thanks in advance, prem
    premm
    last modified by premm
  • TVF drc check

    Hi All,   I've encounter a problem, I'm doing some custom check operation as follows,   1. reduce boundry 5 micron 2. and all layer with reduced 3. then dump m1 and allreduced as gds. I've done all, but ...
    lakshmi.prashanth
    last modified by lakshmi.prashanth
  • Impact of command 'GOLDEN'

    Hello, Today I want to talking about setting GOLDEN cell in DRC.   I put SRAM golden cell in Calibre nmDRC by   1. <"LAYOUT PATH "$LAYOUT_PATH" "SRAM.GoLd.gds">  2. <"LAYOUT PATH "$LAYOUT_...
    jaelin.lee
    last modified by jaelin.lee
  • Layout Depth,

    Hi All,   I'm writing and drc script to do some custom checks as follows, But i'm not getting porper commands,   Purpose: To check wether prboundry(ex: layer 108)  is exsiting in toplevel & to che...
    lakshmi.prashanth
    last modified by lakshmi.prashanth
  • How to change background ICStation 2006.2a from black to white

    Hello I'm user of mentor graphics ICstation 2006.2a. I want to ask question and help, "How to change background window ICStation 2006.2a from black to white?". I want to capture my layout from my monitor to insert in...
    robbyku13
    last modified by robbyku13
  • ldl_methodology.tcl

    dfm::write_rdb -layer { sec_esd_seed_shapes_bad_out } -file TSMC.ESD.LUP.rdb \   On the line above I would like to change the file name TSMC.ESD.LUB that is set at the top level of the rules. WE make make many ...
    billy
    created by billy
  • PERC RDB output

    Where would I find the format of the .RDB file output by PERC.
    billy
    last modified by billy
  • Possible version conflict

    I'm trying to get the ESD checker to run that was given to us from our foundry. Their example will only run if I comment out the following 3 lines proc Export_pad_path_preprocess {} {      ...
    billy
    last modified by billy