• Calibre installation error

    I am trying to install Mentor Calibre on a new server but I can't install it successfully because of the error below.    The most recent version of MIP is already installed in: /home/EDA/mentor/install.ixl ...
    maruko
    created by maruko
  • How to generate calibre view from PEX result

    Hi,   How can I generate calibre veiw from the PEX netlist ( **.pxi ,  **pex.netlist and **.pex) ? I tried in the RVE window by tools-> ExportCalibreview. But I got an error message of " Incorrect MASK ...
    conghaolin
    created by conghaolin
  • Check polygons

    Should the option "Select" select/highlight the polygons failed in the on/offgrid test? But I could not see that happening.
    jarkky
    last modified by jarkky
  • -TVF in Calibre Interactive control file

    Could you pls. clarify, how we can use variable from CUSTOM::DEFINE in TVF code? For example if I wrote: CUSTOM::DEFINE -name MyVar -boolean 1 -select 0 -enable 1\ -prompt "This my var" -tool DRC -tvf 1   ...
    med_an
    last modified by med_an
  • Calibre PERC_LDL P2P check

    Hello,   I am working on Calibre PERC tool and I wanted to know whether the LDL checks can be done on only Full chip or can we also apply this LDL checks on block level and if so how can we extact the pin pairs ...
    mounica
    last modified by mounica
  • How to open socket for icrve from excel?

    How to open socket for icrve from excel? Let's say the RVE result is loaded into excel and need be highlighted in the pyxis layout.
    jarkky
    last modified by jarkky
  • $resize() seem to have effect to selected objects count with negative resize

    I'm making this operation: 1.) $resize(caminsc, void, void, @nocopy); 2.) $merge(@shape); // Here it looks like the negative value resize will "unselect" undesirably some of the shapes !!! 3.) $resize(-caminsc, vo...
    jarkky
    last modified by jarkky
  • I am trying to simulate Monte carlo analysis but getting below error, can someone please help me

    ** Error: (eldo-63) In file "./DESIGN__13812_0TMP" line 24: + Unable to include file "\\dlg1th4s2\MODELS_LIBRARY\APN_MODEL_DATA\resistor\resistor\resistor.lib". ** Warning: (eldo-46) In file "C:\DPH_SVLIBS\SpiceLibrar...
    a_kumar_ok40u
    created by a_kumar_ok40u
  • SV Queue Questa Waveform Display

    Mentor Questa Simulator   I am tying to display a System Verilog Queue in the waveform window (data_q[$]), but I get this message   # (vsim-4027) Logging is not supported for Queue item   Is there a ...
    t_ewins_qqrov
    created by t_ewins_qqrov
  • work empty

    i'm using modelSIM and i have a problem with work library everytime i compile my file my work library says its empty hoe can i solve this problem
    uruk
    last modified by uruk
  • Issue with SystemC DPI tfdb file [ vsim error-2178 "A newer version (version 11) SystemC DPI tfdb file is present in current work library. The software only expects tfdb file with version 10 or below"]

    I have a perl script which has the below questasim line of code in it:- //////////////////////////////////////////////////         ...       ... &#...
    ramees041
    last modified by ramees041
  • Simulation error due to Non-convergence

    how to resolve #convergence problems: There are some very #small-resistors which can cause non-convergence They are: X1I4594.R14 1.400000e-012 X1I4627.R14 1.400000e-012 X1I57.R1 4.200000e-010 REX1I103.Q1 1.000000e-00...
    a_kumar_ok40u
    created by a_kumar_ok40u
  • Issue with real number constraint in  Questasim simulation

    There is Issue with   constraint   which is declared as real in SV with 10.3d_1 Compiler 2014 .The issue is not present with new version ie 2019 series . Can you share some  way to  ...
    ryst
    created by ryst
  • Oasys  Retiming Operations: Is it possible for  pipeline registers to be  automatically pushed through the combinational logic accross module hierarchy ?

    Hi ,  I am using first time Oasys Retiming Operations and my RTL is hierarchical.   Is it possible to   include pipeline registers inserted in the RTL, top module and to achieve,  ...
    t_ilic_lrmjb
    last modified by t_ilic_lrmjb
  • Questa vsim +nosdferror option , is it dangerous to use ?

    Hi,  I have a question about gate level simulation with back annotation using Questa.   As described in Questa manuals, I have a situation that I cannot start simulation because of errors by the SDF annota...
    t_ilic_lrmjb
    last modified by t_ilic_lrmjb
  • showing "missing ports" in RVE,

    showing "missing ports" in RVE, I have checked the layer map file its mapped correctly still I could not able to find the solution.can anyone help here?
    mahesh_gunde1
    last modified by mahesh_gunde1
  • Does tessent support mram bist insertion?

    Does tessent support mram bist insertion now?
    a_liu_jmqzi
    created by a_liu_jmqzi
  • ERROR: Error ..undefined layer name parameter: ERC_ESDBJT_FLTPW.

    Hi all,  I am a newbie in Calibre LVS checking.  Today, when I check LVS for an IP with BCD1370 Calibre LVS version 1.9.4.1, the execution could not complete due to the error below: ERROR: Error RES2 on l...
    khanhlinh
    last modified by khanhlinh
  • About *.tcelllib library format

    Hi, I see an instruction for starting flow with tessent on mentor website as follows: Link : Siemens Digital Industry Software: Sign In  set_context dft -rtl read_cell_library ../library/adk.tcelllib set_d...
    n_pham_dacxw
    created by n_pham_dacxw
  • Writing out extracted net into one GDS

    Hi, I'm trying to write out extracted net geometries into a single gds but Calibre does not compile.  I need to suffix the cell to differentiate based on the nets and that is probably what it does not like. ...
    i_pakkirisamy_wkmgq
    last modified by i_pakkirisamy_wkmgq