• I am trying to simulate Monte carlo analysis but getting below error, can someone please help me

    ** Error: (eldo-63) In file "./DESIGN__13812_0TMP" line 24: + Unable to include file "\\dlg1th4s2\MODELS_LIBRARY\APN_MODEL_DATA\resistor\resistor\resistor.lib". ** Warning: (eldo-46) In file "C:\DPH_SVLIBS\SpiceLibrar...
    a_kumar_ok40u
    created by a_kumar_ok40u
  • SV Queue Questa Waveform Display

    Mentor Questa Simulator   I am tying to display a System Verilog Queue in the waveform window (data_q[$]), but I get this message   # (vsim-4027) Logging is not supported for Queue item   Is there a ...
    t_ewins_qqrov
    created by t_ewins_qqrov
  • work empty

    i'm using modelSIM and i have a problem with work library everytime i compile my file my work library says its empty hoe can i solve this problem
    uruk
    last modified by uruk
  • Issue with SystemC DPI tfdb file [ vsim error-2178 "A newer version (version 11) SystemC DPI tfdb file is present in current work library. The software only expects tfdb file with version 10 or below"]

    I have a perl script which has the below questasim line of code in it:- //////////////////////////////////////////////////         ...       ... &#...
    ramees041
    last modified by ramees041
  • Simulation error due to Non-convergence

    how to resolve #convergence problems: There are some very #small-resistors which can cause non-convergence They are: X1I4594.R14 1.400000e-012 X1I4627.R14 1.400000e-012 X1I57.R1 4.200000e-010 REX1I103.Q1 1.000000e-00...
    a_kumar_ok40u
    created by a_kumar_ok40u
  • Issue with real number constraint in  Questasim simulation

    There is Issue with   constraint   which is declared as real in SV with 10.3d_1 Compiler 2014 .The issue is not present with new version ie 2019 series . Can you share some  way to  ...
    ryst
    created by ryst
  • Oasys  Retiming Operations: Is it possible for  pipeline registers to be  automatically pushed through the combinational logic accross module hierarchy ?

    Hi ,  I am using first time Oasys Retiming Operations and my RTL is hierarchical.   Is it possible to   include pipeline registers inserted in the RTL, top module and to achieve,  ...
    t_ilic_lrmjb
    last modified by t_ilic_lrmjb
  • Questa vsim +nosdferror option , is it dangerous to use ?

    Hi,  I have a question about gate level simulation with back annotation using Questa.   As described in Questa manuals, I have a situation that I cannot start simulation because of errors by the SDF annota...
    t_ilic_lrmjb
    last modified by t_ilic_lrmjb
  • showing "missing ports" in RVE,

    showing "missing ports" in RVE, I have checked the layer map file its mapped correctly still I could not able to find the solution.can anyone help here?
    mahesh_gunde1
    last modified by mahesh_gunde1
  • Does tessent support mram bist insertion?

    Does tessent support mram bist insertion now?
    a_liu_jmqzi
    created by a_liu_jmqzi
  • ERROR: Error ..undefined layer name parameter: ERC_ESDBJT_FLTPW.

    Hi all,  I am a newbie in Calibre LVS checking.  Today, when I check LVS for an IP with BCD1370 Calibre LVS version 1.9.4.1, the execution could not complete due to the error below: ERROR: Error RES2 on l...
    khanhlinh
    last modified by khanhlinh
  • About *.tcelllib library format

    Hi, I see an instruction for starting flow with tessent on mentor website as follows: Link : Siemens Digital Industry Software: Sign In  set_context dft -rtl read_cell_library ../library/adk.tcelllib set_d...
    n_pham_dacxw
    created by n_pham_dacxw
  • Writing out extracted net into one GDS

    Hi, I'm trying to write out extracted net geometries into a single gds but Calibre does not compile.  I need to suffix the cell to differentiate based on the nets and that is probably what it does not like. ...
    i_pakkirisamy_wkmgq
    last modified by i_pakkirisamy_wkmgq
  • Undefine module issue in Gatelevel design flow

    Hi,   I have a problem when using the Gate level design flow with tessent.     + My flow is below: set_context dft -no_rtl read_liberty standard_cell.lib read_liberty macro1.lib   read_verilo...
    n_pham_dacxw
    created by n_pham_dacxw
  • How to find floating metals in layout using SVRF?

    How to find floating metals (metals that are not connected to diffusion or poly or pins) in layout using SVRF? 
    sharu
    last modified by sharu
  • how to define drawing layer as a pin

    Hi i want to define drawing layer also as a pin.   example below is the way i assign metal text as a pin   /////////////////////////////// // Map TEXT layer to port names /////////////////////////////// TE...
    mfaisalazri@gmail.com
    last modified by mfaisalazri@gmail.com
  • How to make lvs recognize metal drawing as text rather use text drawing.

    hi    i have this issue, lvs not recognize AA6 as a pin because it use same layer metal1 drawing same goes to the rectangle metal 1 drawing. in my lvs rules deck I add new line to make sure lvs recognize...
    mfaisalazri@gmail.com
    last modified by mfaisalazri@gmail.com
  • how to add metal layer

    Hi I write this script but its wrong some where please advice?   /////////////////////////////////// // LAYER DERIVATIONS AND OPERATIONS /////////////////////////////////// //----------------------------- // Defi...
    mfaisalazri@gmail.com
    last modified by mfaisalazri@gmail.com
  • DFM PROPERTY in LVS command file

    Dear All,   There is a message when I running LVS:   //  Applying licensing  policy... //  calibrehlvs license  acquired. //  calibrelvs license  acquired.   //  Warn...
    andrewng
    last modified by andrewng
  • how to extract cc between TSV and SI

    hi,guys   how to extract cc between SI and TSV with ox insulator = {{0.2,4.1}} ?  I build the mipt but didn't extract any capacitance between them. I state "PEX MAP substrate SI" and "CONNECT SI", and att...
    leo_gan0216
    last modified by leo_gan0216