• Calibre lvs signature for inductor

    I am creating signature file for Inductor. when i run "create_signature" i am getting following error. "Cannot establish connectivity of this layer in the MASK connectivity set: metal6"
    bharath2k4er
    last modified by bharath2k4er
  • LVS BLACK BOX PORT

    Hi all,   I am trying to run the lvs with partial gds of some IP, but  I am having "Layout extra pin" and "Source extra pin" issues in a IP with LVS BOX statement. And I have known that Calibre can use ...
    fangjuan
    last modified by fangjuan
  • Overflow pointing to Pwell

    I making a GDI adder for my pipelined multiplier and I came across overflow that I cannot resolve. I think its mainly due to the lack of knowledge, but please help me here. The overflow that points from the Metal1 to ...
    ivanaleksyeyenko
    created by ivanaleksyeyenko
  • LVS Different number of ports

    Hi! LVS is giving me different number of ports, even though I auto-placed ports, Autoflorplan, and auto-placed the standard cells. I decided to check this on a small design of just an AND gate and the same thing came ...
    ivanaleksyeyenko
    last modified by ivanaleksyeyenko
  • DSPF extract with a extra resistance

    Below is DSPF extract by calibre,R0 is extracted with a extra resistance  "1338 ",so how can ignore it by setup? I do not need this parameter in dspf. I need the format of R1 like.   *|DSPF 1.5 * ...
    hu_qy
    created by hu_qy
  • Net name size global modification

    I need use Xpedition Designer V.X 2.4 modify a schematic, I found that the previous schematic net name size is some 2.00mm and some is 2.54mm. I want to know how to set the size so that they can be exactly the same. &...
    brantgu
    created by brantgu
  • what options in v2lvs make the different pin format in the output netlist?

    what options in v2lvs make the different pin format in the output netlist? one is: Xsw_cnm/runit_top_wrap/runit_top/runit_rams_top/BOOTROM_48KB_boot_rom/tsmc_12nm_rom_rom0 + FE_OFN1017130_sw_cnm_runit_top_wrap_runi...
    lingwan
    created by lingwan
  • Question about Calibre PEX Warnings

    I met some WARNING problems when I run Caliibre PEX. Does these Warnings lead to the final results error?  Which warnings are unnecessary to modify? 
    renjianfenggg
    last modified by renjianfenggg
  • Poly as routing layer

    In my layout, I dont want Poly as routing layer. How can I use DRC to detect the Polys.
    hu_qy
    created by hu_qy
  • Calibre LVS giving Short circuit warnings and LVS shorts, but the Comparison results are clean

    I am running Calibre LVS. In my design I have some pins which are shorted to VDD or to GND. In the netlist generated it uses the *.CONNECT statement to do the same.         *.CONNECT out1 VSS ...
    varunmj
    last modified by varunmj
  • LVS_calibre

    Hi guys I have just begin using Mentor Graphics  and I find it difficult to run the LVS. The following warnings appear: Warning: # 1 in int_2 WARNING: Invalid PATHCHK request "! POWER": no POWER nets present, o...
    edsonps
    last modified by edsonps
  • Calibre DRC: Unique Concatenation value of text labels

    I was having some issues trying to find a closure to the DRC algorithm: Not sure if combination of DFM TEXT and other commands can solve this?   There is one text label say("X") on each Layer1 polygon There is ...
    samk
    last modified by samk
  • Monte Carlo Analysis Help needed..

    I am facing trouble with running montecarlo analysis in Pyxis schematic entry, i am trying to do a simple experiment of a CMOS inverter dc sweep analysis. I need to perform monte carlo simulations for this test bench....
    ph10pe04
    last modified by ph10pe04
  • DFM Fill optimization to prefer avoiding shapes on a different layer

    Hi, I'm trying to create a custom fill procedure with Calibre, using DFM Fill (and its friends).  I would like to discourage (but not prohibit) Calibre from filling one layer in the same area where another l...
    tross
    last modified by tross
  • Calibre view generation with 2017 version is throwing the following error.

    HI,   My calibre tool version is updated from 2013.2_18.13  to 2017.3_29.23 recently.Calibre PEX view generation with 2017.3_29.23  is throwing the following error     'Calibre view genera...
    anandmohancec
    last modified by anandmohancec
  • Calibre LVS - excluding standard cell from lvs

    Hi I am using Calibre for verification and I am new to Calibre. I am trying to run LVS for a chip layout. There are standard cells and IO pads in the design. I have given the Layout as gdsii and schematic as cdl...
    varunmj
    last modified by varunmj
  • How to get polygon coordinate (SVRF)

    Hello,   Design Manual team has added a rule where we should check coordinates of polygon 's extent; I know I must use DFM PROPERTY but I'm stuck...I am able to get polygon's extent, I can also get small po...
    chris_st
    last modified by chris_st
  • Back annotation for wire RC

    Hi, I have got the RC extraction values from PEX simulation. My testing circuit is very simple and there is a difference between schematic and post-layou simulation due to wire RC. So I subsititute wire RC back to my...
    popoyoho
    last modified by popoyoho
  • how to use foreach loop in calibre svrf, using tvf::commands?

    Hi,   I want to use foreach loop in calibre svrf coding. I know that it can be done using tvf. May i Know the syntax to use foreach loop in svrf coding.   Thanks, Venkatesh
    venkateshwarlu
    last modified by venkateshwarlu
  • Two questions about testing with HDL designer

    Hello,   1. I have successfully created a test bench with HDL designer, and I use Modelsim to simulate. By pressing the Modelsim icon and selecting "through components" I can simulate my design. My question is ...
    talnaim
    created by talnaim