• Monte Carlo Analysis Help needed..

    I am facing trouble with running montecarlo analysis in Pyxis schematic entry, i am trying to do a simple experiment of a CMOS inverter dc sweep analysis. I need to perform monte carlo simulations for this test bench....
    last modified by ph10pe04
  • DFM Fill optimization to prefer avoiding shapes on a different layer

    Hi, I'm trying to create a custom fill procedure with Calibre, using DFM Fill (and its friends).  I would like to discourage (but not prohibit) Calibre from filling one layer in the same area where another l...
    last modified by tross
  • Calibre view generation with 2017 version is throwing the following error.

    HI,   My calibre tool version is updated from 2013.2_18.13  to 2017.3_29.23 recently.Calibre PEX view generation with 2017.3_29.23  is throwing the following error     'Calibre view genera...
    last modified by anandmohancec
  • Calibre LVS - excluding standard cell from lvs

    Hi I am using Calibre for verification and I am new to Calibre. I am trying to run LVS for a chip layout. There are standard cells and IO pads in the design. I have given the Layout as gdsii and schematic as cdl...
    last modified by varunmj
  • How to get polygon coordinate (SVRF)

    Hello,   Design Manual team has added a rule where we should check coordinates of polygon 's extent; I know I must use DFM PROPERTY but I'm stuck...I am able to get polygon's extent, I can also get small po...
    last modified by chris_st
  • Back annotation for wire RC

    Hi, I have got the RC extraction values from PEX simulation. My testing circuit is very simple and there is a difference between schematic and post-layou simulation due to wire RC. So I subsititute wire RC back to my...
    last modified by popoyoho
  • how to use foreach loop in calibre svrf, using tvf::commands?

    Hi,   I want to use foreach loop in calibre svrf coding. I know that it can be done using tvf. May i Know the syntax to use foreach loop in svrf coding.   Thanks, Venkatesh
    last modified by venkateshwarlu
  • Two questions about testing with HDL designer

    Hello,   1. I have successfully created a test bench with HDL designer, and I use Modelsim to simulate. By pressing the Modelsim icon and selecting "through components" I can simulate my design. My question is ...
    created by talnaim
  • TSMC 65nm PDK CRN65 with Calibre LVS/DRC/PEX

    My main questions have to do with the differences between the flow of doing LVS/DRC/PEX for Analog Design (ie. opamp layout and other analog circuits) vs. the RFIC flows (LNA, Mixer etc) where the foundry modelled pce...
    last modified by growingmind
  • calibre LVS and ERC

     Hello i have encountered this problem when running LVS, i have checked the license and  it is working properly , any idea ? //  ERROR: The following products could not be licensed sufficiently: //...
    last modified by moustafa_ali
  • MOS connected to both power and ground

    MOS connected to both power and ground. This is an ERC getting in my design . But my design is LVS clean . I check ed manually , there are no devices ( source ) connected to both Power and ground.    When w...
    created by chikku
  • Fatal error: Rules must contain capacitance order statement in caliber while running pex

    I am getting the error as Fatal error: Rules must contain capacitance order statement in caliber while running pex as shown above
    last modified by prashanthk
  • Best way to write regress script for UVM TB(for questasim)

    I am new to scripting.  I have module/top level UVM testbenches. I am using questasim for simulation. I have tcl scripts to run the simulations. I am running simulation in GUI mode. I want to come up with script...
    last modified by uvmsd
  • svdb database not created in LVS/PEX

    Hi all,   I need to generate svdb database in LVS/PEX process. LVS passed and got a smile, but svdb database is never generated well   The error message is: " Error 179: Error reading file "svdb/ltx_m200...
    last modified by iantsai
  • How do I use a setup pattern when generating a test pattern in tessent.

    I am designing a mixed signal SOC where the SMPS must be switched on before scan and MBIST.  In my SOC simulation testcase I shift in a pattern to control the SMPS through JTAG. How do I add that pattern when ge...
    created by imc_user8
  • How can I plot the phase noise of an Oscillator?

    I have used the following code from Eldo RF User's Manual (My oscillation frequency is 1.7MHz and was running fine in .TRAN analysis)   .op * Steady-state analysis for autonomous circuit .sst oscil nharm_osc1=1...
    last modified by roy_baidyanath
  • How can we translate a particular text labels by its net name?

    Hi,   How can we translate a particular text labels by its net name. Example: If we want to translate the all vss labels as a calibre gdsii output, how can we implement this.   Thanks and regards Pulakanti S...
    last modified by psandeep
  • Calibre LVS missing inductor (bad device detected)

    Hello All, I am new to calibre and I am facing a problem about "missing inductor" and I have been trapped for a while. At the very beginning, I was about to build a basic LC based bandpass filter layout. When I pass...
    last modified by popoyoho
  • Is there a way i can do NET BASED XOR comparison?

    I wanted to compare only the specified NETs between the 2 GDS. Is there any way to do that using XOR?
    last modified by vnerella568
  • Calibre/LVS/ Device statement

    Hello, Can I represent two different device elements/models with the same layer in lvs? I have a device represented by layer"RR" with terminals represented by derived layers "pos" and "neg". Originally, that stack ...
    last modified by samer1