• Calibre Pex R+C+CC  extraction

    Hi All,   What is the difference between  C and CC parasitics in a Pex  R+C+CC extraction.    As far I know, CC is coupling cap. i.e capacitance between particular net to a neighbouring net ...
    last modified by anandmohancec
  • Issue with random number generation: artifacts in gaussian distributions

    The issue is as the title says. I'm getting some weird artifacts when I generate random numbers with a gaussian distribution. It seems like certain bins of numbers are being generated more often than others while some...
    created by v_govind_bdepz
  • Calibre cannot type in GUI

    I have an issue when I open calibre and try to run drc/lvs/xrc. The dialog box opens but I cannot type, meaning the application is not accepting input from the keyboard. The mouse works fine, allowing to navigate thro...
    last modified by dan_dmea
  • Running Calibre DRC on DEF from INNOVUS

    Hi All,   I want to run Calibre signoff DRC check for the DEF that is extracted from INNOVUS. I have the GDS present for all the IP's that are used in the design. Please let me know the correct approach for thi...
    last modified by newbie_3
  • Modelsim/Questasim unit delay simulation

    I would like to launch an unit delay RTL simulation using Questasim 10.1. I ve look how to compile the design and i see there is an option +delay_mode_unit for compiling verilog files. My design is vhdl. Is there an o...
    created by mxm89
  • .PZ data

    I have run a .PZ stability analysis and have got the data in terms of poles and zeros as shown below. POLES       MODULUS           ...
    created by kooshar
  • Error in eldo simulation when running with premier + multi-thread

    Hi,   I encounter the simulation error when I try to run eldo simulation with premier and multi-thread, here is how I submit the command to the server:   bsub  -q reg -R "rh60" -P xxxx -Ip -n 4 e...
    created by ktlee
  • Tessent: scan chain elements/families to include when defining scan modes

    In the example given for clubbing all OCC scan elements under 1 scan mode, 2 scan chain families are included in the add_scan_mode like so (see last command):   >register_attribute -name is_occ -obj_type scan...
    created by vijay82
  • Compare technology lef and calibre drc rule file

    Hi,  Is there a method or tool available to compare the technology lef file and the calibre DRC rule file to find any mismatches?   Thanks and Regards     Varun M J
    created by varunmj
  • User of centering in LCell_MakeLogo function

    Hello Everyone   Probably a very basic question. However, I have some problems making the centering of text work when using the LCell_MakeLogo function in a T-Cell The L-Edit manual says the following.   ...
    last modified by tom.larsen@epfl.ch
  • Why Calibre gives compilation error in -flat mode?

    If I run Calibre with the -flat switch I get the following message:   ERROR: FLAT COMPILER Error on line 0 of <my_path>/<my_file>.rsf - 5421 forbidden operations present   If I run the same set...
    last modified by analogmatch
  • Calibre lvs signature for inductor

    I am creating signature file for Inductor. when i run "create_signature" i am getting following error. "Cannot establish connectivity of this layer in the MASK connectivity set: metal6"
    last modified by bharath2k4er

    Hi all,   I am trying to run the lvs with partial gds of some IP, but  I am having "Layout extra pin" and "Source extra pin" issues in a IP with LVS BOX statement. And I have known that Calibre can use ...
    last modified by fangjuan
  • Overflow pointing to Pwell

    I making a GDI adder for my pipelined multiplier and I came across overflow that I cannot resolve. I think its mainly due to the lack of knowledge, but please help me here. The overflow that points from the Metal1 to ...
    created by ivanaleksyeyenko
  • LVS Different number of ports

    Hi! LVS is giving me different number of ports, even though I auto-placed ports, Autoflorplan, and auto-placed the standard cells. I decided to check this on a small design of just an AND gate and the same thing came ...
    last modified by ivanaleksyeyenko
  • DSPF extract with a extra resistance

    Below is DSPF extract by calibre,R0 is extracted with a extra resistance  "1338 ",so how can ignore it by setup? I do not need this parameter in dspf. I need the format of R1 like.   *|DSPF 1.5 * ...
    created by hu_qy
  • Net name size global modification

    I need use Xpedition Designer V.X 2.4 modify a schematic, I found that the previous schematic net name size is some 2.00mm and some is 2.54mm. I want to know how to set the size so that they can be exactly the same. &...
    created by brantgu
  • what options in v2lvs make the different pin format in the output netlist?

    what options in v2lvs make the different pin format in the output netlist? one is: Xsw_cnm/runit_top_wrap/runit_top/runit_rams_top/BOOTROM_48KB_boot_rom/tsmc_12nm_rom_rom0 + FE_OFN1017130_sw_cnm_runit_top_wrap_runi...
    created by lingwan
  • Question about Calibre PEX Warnings

    I met some WARNING problems when I run Caliibre PEX. Does these Warnings lead to the final results error?  Which warnings are unnecessary to modify? 
    last modified by renjianfenggg
  • Poly as routing layer

    In my layout, I dont want Poly as routing layer. How can I use DRC to detect the Polys.
    created by hu_qy