• How to get polygon coordinate (SVRF)

    Hello,   Design Manual team has added a rule where we should check coordinates of polygon 's extent; I know I must use DFM PROPERTY but I'm stuck...I am able to get polygon's extent, I can also get small po...
    chris_st
    last modified by chris_st
  • how to use foreach loop in calibre svrf, using tvf::commands?

    Hi,   I want to use foreach loop in calibre svrf coding. I know that it can be done using tvf. May i Know the syntax to use foreach loop in svrf coding.   Thanks, Venkatesh
    venkateshwarlu
    last modified by venkateshwarlu
  • Two questions about testing with HDL designer

    Hello,   1. I have successfully created a test bench with HDL designer, and I use Modelsim to simulate. By pressing the Modelsim icon and selecting "through components" I can simulate my design. My question is ...
    talnaim
    created by talnaim
  • Back annotation for wire RC

    Hi, I have got the RC extraction values from PEX simulation. My testing circuit is very simple and there is a difference between schematic and post-layou simulation due to wire RC. So I subsititute wire RC back to my...
    popoyoho
    created by popoyoho
  • TSMC 65nm PDK CRN65 with Calibre LVS/DRC/PEX

    My main questions have to do with the differences between the flow of doing LVS/DRC/PEX for Analog Design (ie. opamp layout and other analog circuits) vs. the RFIC flows (LNA, Mixer etc) where the foundry modelled pce...
    growingmind
    last modified by growingmind
  • calibre LVS and ERC

     Hello i have encountered this problem when running LVS, i have checked the license and  it is working properly , any idea ? //  ERROR: The following products could not be licensed sufficiently: //...
    moustafa_ali
    last modified by moustafa_ali
  • How to get the pin order wanted in my extraction netlist from Calibre xRC?

      How to get the pin order wanted in my extraction netlist from Calibre xRC?    
    karen_chow
    last modified by karen_chow
  • MOS connected to both power and ground

    MOS connected to both power and ground. This is an ERC getting in my design . But my design is LVS clean . I check ed manually , there are no devices ( source ) connected to both Power and ground.    When w...
    chikku
    created by chikku
  • Fatal error: Rules must contain capacitance order statement in caliber while running pex

    I am getting the error as Fatal error: Rules must contain capacitance order statement in caliber while running pex as shown above
    prashanthk
    last modified by prashanthk
  • Best way to write regress script for UVM TB(for questasim)

    I am new to scripting.  I have module/top level UVM testbenches. I am using questasim for simulation. I have tcl scripts to run the simulations. I am running simulation in GUI mode. I want to come up with script...
    uvmsd
    last modified by uvmsd
  • svdb database not created in LVS/PEX

    Hi all,   I need to generate svdb database in LVS/PEX process. LVS passed and got a smile, but svdb database is never generated well   The error message is: " Error 179: Error reading file "svdb/ltx_m200...
    iantsai
    last modified by iantsai
  • How do I use a setup pattern when generating a test pattern in tessent.

    I am designing a mixed signal SOC where the SMPS must be switched on before scan and MBIST.  In my SOC simulation testcase I shift in a pattern to control the SMPS through JTAG. How do I add that pattern when ge...
    imc_user8
    created by imc_user8
  • How can I plot the phase noise of an Oscillator?

    I have used the following code from Eldo RF User's Manual (My oscillation frequency is 1.7MHz and was running fine in .TRAN analysis)   .op * Steady-state analysis for autonomous circuit .sst oscil nharm_osc1=1...
    roy_baidyanath
    last modified by roy_baidyanath
  • How can we translate a particular text labels by its net name?

    Hi,   How can we translate a particular text labels by its net name. Example: If we want to translate the all vss labels as a calibre gdsii output, how can we implement this.   Thanks and regards Pulakanti S...
    psandeep
    last modified by psandeep
  • Calibre LVS missing inductor (bad device detected)

    Hello All, I am new to calibre and I am facing a problem about "missing inductor" and I have been trapped for a while. At the very beginning, I was about to build a basic LC based bandpass filter layout. When I pass...
    popoyoho
    last modified by popoyoho
  • Is there a way i can do NET BASED XOR comparison?

    I wanted to compare only the specified NETs between the 2 GDS. Is there any way to do that using XOR?
    vnerella568
    last modified by vnerella568
  • Calibre/LVS/ Device statement

    Hello, Can I represent two different device elements/models with the same layer in lvs? I have a device represented by layer"RR" with terminals represented by derived layers "pos" and "neg". Originally, that stack ...
    samer1
    last modified by samer1
  • Can we use for loop or foreach commands after "OR" command in tvf?

    Hi  Can we use  for loop or foreach commands after "OR" command in tvf?   Example: I want to implement below svrf command using tvf. MYOBJ = OR M0_DRW M1_DRW M2_DRW M3_DRW   I have tried below...
    psandeep
    last modified by psandeep
  • In TVF/SVRF, how can I select just pins that fall on design boundary?

    Hello, I am writing some DRC code that I want to output markers for all pins that are on the boundary of the design layout. The boundary has its own layer that is a rectangle that fills the entire design, so the edge...
    max229
    last modified by max229
  • Calibre - Check to highlight if a Gate does not connect to P-diff

    I would like a simple check to highlight nets which connect only to gate(s) (n and/or p) and only ntype S/D diffusion. I am not sure which way to address it 
    mattb73
    last modified by mattb73