• Create dynamic DRC run directory

    Hi,   I'd like to create a dynamic named DRC run directory when loading Calibre Interactive. For example, a run directory output folder with the following naming format:      <layoutviewn...
    last modified by rachel.spykerman
  • Understanding oasys warnings and TA messages

    Is there a document that describes the meaning of all Oasys warnings and a table listing what possible actions to take with respect to TA- messages? Also on the synthesis log, I see that oasys reports a lot of inform...
    last modified by schuler1
  • verilog hierarchy syntax

    Hi all,   Could you please tell how to describe the following hierarchy so that Questa can recognize?     I've used the hierarchy in do file:   tcheck_set ***.dfi_top_wrapper_U0/\RC_CG_HIER_INST...
    created by jol
  • Help with FATAL ERROR: Rules file must contain a CAPACITANCE ORDER statement

    In my current pdk, I do not have a CAPACITANCE ORDER statement in my rules file for CalibrexRC. Is there an example of this statement I can add to my rules file to enable a PEX verification run?   Currently usi...
    last modified by aguzman
  • periodic ac analysis in mentor design architect-ic

    Hi all,   I'm using mentor design architect v2008.2_7.1 to simulate a switched capacitive filter. As you know, I need to utilize periodic AC analysis rather than "normal" AC analysis. Even if there are some prov...
    last modified by e3402
  • ERROR(130): Incorrect MASK SVDB DIRECTORY options for this function.

    Hi All, I am doing a Calibre query using this command for QRC. calibre2017 -query /home/marben/GF55/GF_stuff/Components/cmos10lpe_CDS_oa_dl064_15_20170731/DRC_LVS_Run_Area/svdb pcd_inv_L -query_input query_cmd | tee...
    last modified by marben.orallo
  • Hierarchy LVS problem when using xcells to do hierarchical extraction

    Hi everyone,   I want to use hierarchical extraction for my design. I run LVS alone with hcells and it is right. But when I use the same hcells to run LVS in xRC, it turns out that my LVS is wrong. I set the hce...
    created by jiaqi
  • Error with Calibre PEX using IBM PDK

    Hello,   This is an update from my previous message in this community: https://communities.mentor.com/thread/22601   I am now using an updated version of Cadence (1.6.7.b where b = base version) and an up...
    last modified by growingmind
  • Questa formal - synchronizing signals

    hi i'm using Questa formal tool Version 10.7b_1. my question is: is there a way to force all signals to sync with the posedge of a clock (some "netlist" or anything else)?   thanks, Gidon 
    last modified by gid
  • Calibre LVS: How to compare the intrinsic diode (parasitic diode btw nwell & psub) area in LVS?

    Hi I'm trying to extract the intrinsic Nwell- Psub diode area for accurate modelling. How can I make Calibre LVS to recognise the intrinsic diodes and compare the diode area against a schematic model?   Thanks.
    last modified by kkmovva
  • Xilinx libsystemctlm-soc support with Questa 2019.1

    Hello,   I’m trying to put in place a QEMU/TLM co-simulation environment with Questa 2019.1 for Xilinx Zynq-7000 platform. For this purpose, Xilinx provides the libsystemctlm-soc library which is basically...
    last modified by vincentlenoir
  • Calibre drc execution using multiple drc rule files

    Hi,   I have 3 different calibre drc rule files ( one main drc rule deck and 2 patch files), which I am currently running 3 times to verify my block. Is there any way that I can run all the 3 rule files in one s...
    last modified by anandmohancec
  • create SRPG pattern with EDT

    how to create SRPG pattern with EDT enabled
    last modified by ycjiao1982
  • LVS BOX does not bypass subckt for custom cell

    To whom it may concern,   I have designed my own inductor using EMX with ports and an extracted DC model of a resistor between the IN and OUT ports of the inductor.   My process includes a RES layer whic...
    last modified by rcy22
  • instantiation input value

    hi everyone i need some help to understand some problem, the compiler don't refer to the value in the parentheses.   i.e: "xxxxx"  module name ( clock  ( any input ), ... ... )   for "any input" ...
    last modified by daviddadush
  • Simulating Vivado IP in Questa

    Hi, I have a project in Vivado 2017.3 with Vivado IP in the design. The simulation script for Questa is also generated by the tool.  .... \project_1\project_1.ip_user_files\sim_scripts\design_1 The complete ...
    last modified by joniengr081
  • Calibre RVE Highlighting Errors with particular colors

    Hi I am using the following RVE settings   from Cadence Virtuoso I am loading Calibre RVE . I have only 4 different errors/rule checks violations which needs to be highlighted in 4 different colors.(I am load...
    last modified by cad_lj
  • HDL Designer Altera Megawizard problem

    Hello all,   I would like to add "Tri-speed-ethernet" IP to HDL Designer that I generated from Altera Megawizard. I used the flow inside the HDL Designer and imported my IP variation file but when I try to make ...
    last modified by rdemirci
  • RVE DRC 'Check Text' column - hide rule file pathname?

    The 'check text' column seems to always show the rule file pathname, once for each row / for each rulecheck.  This takes up a lot of real estate on the screen.  Is there a way to show the check text column w...
    last modified by tomgrundy
  • Error with Calibre DRC/PEX using IBM PDK

    Hello,   I am using a fairly recent IBM PDK with Calibre 2011 and Cadence IC6.1.4 - both of which are fairly old, probably before the PDK was created.   PDK says it was tested with Cadence IC6.1.7 and Cali...
    last modified by growingmind