• How lock symbol in symbol editor?

    Hi, i'm use Symbol Editor Version NSE7.9. How lock the symbol? Thanks
    last modified by gianfranco
  • How Do I Deal With Libraries?

    I am able to edit single schematic library symbols by right-clicking then selecting Symbol> Edit Library Symbol. It seems I can edit individual symbols via an end-around but not open, edit or manage any library, it...
    last modified by melvingalil
  • LVS errors: different number of ports,nets,connectivity errors.

    Hi, my lvs run is done with some errors , and i am not able to debug what exactly the problem is.     Error:    Different numbers of ports.   Error:    Different numbers...
    last modified by arungande
  • Can the Questa CDC reports all synchronization flipflop names?

    Hi, The Questa CDC tool by default is showing the first synchronization flipflop name in the report.  Is there a way to configure the tool to report the first and the second synchronization flipflop? assuming my...
    created by mmffss2007
  • text translation using calibre deck

    How can we translate TEXT layers using a calibre (drc) deck? The usual procedure we use for layer translation is something like LAYER IN_METAL1            3400 L...
    last modified by ema
  • Error: Calibre RHEL 5 enabling environment variable is not set to an appropriate value.

    Hi All, How to fix this error: Error: Calibre RHEL 5 enabling environment variable is not set to an appropriate value.   // Support for Calibre applications running on the RHEL 5 operating system // is extreme...
    last modified by marben.orallo
  • How to run calibre -drc in background

    Hi,     I would like to turn off the ability of the drc run to show the transcript off the run during its run.   Is there a switch for that?     Thanks, Michael
    last modified by michael.shuster
  • Zoom Undo -> how to?

    Hi All,   How can I do 'Undo' to the Zoom command? Pressing 'L' on the keyboard brings me to the 'Last Zoom'. But what about going to the Zoom before a last one, etc?   Thank you!
    created by ldm.eth
  • Finding net length in calibre

    Hi, I need to write rule file to find the length of the net connected to the port.  I've been looking around the manuals but can't find an example.  Would you please help?   Thank you, --Binh Pham
    last modified by binhpham
  • [Questa] $MODEL_TECH -> where is defined? where should point?

    Hi All,   As for the $MODEL_TECH variable, where is it defined? Where should point to?   Thank you!
    last modified by ldm.eth
  • glbl + vcom/vopt/vsim libraries -> when used?

    Hi All,   1) What is the glbl library? What does it include and why needed?   2) What libraries should be loaded with the vsim command? Some libraries should be loaded/compiled with vcom, some of them with...
    created by ldm.eth
  • Layout not recognizing VDD and GND nets; LVS giving discrepancy errors

    Hello,   In Calibre's comparison results, I get four incorrect net discrepancies. Two are complaining that there are no similar nets for vdd and gnd in layout, and two are complaining that "Net 394" and "Net 398...
    last modified by dunn
  • 'Save Project' and 'Save Project As' TCL command

    Hi All,   Is there a Save Project or Save Project As TCL commands in Questa?   If I start a new project with the Questa GUI as 'File -> New -> Project' then there is no a problem - all the Project Se...
    last modified by ldm.eth
  • Error Messages -> is there a manual discribing ALL error messages?

    Hi All, Is there any database or manual, which describes all types of error messages (like vopt-7, vopt-1127, etc)? Thank you!
    last modified by ldm.eth
  • [Questa] Transcript window -> how to set different colors/fonts for the files and directories

    Hi All,   In the Transcript window, how to colorize the listed directories? files?   When I run the 'ls -la' command from the Transcript prompt, the files and directories are displayed with the same color ...
    last modified by ldm.eth
  • how to make lvs clean with different voltage domain ?

    Hi All, I have a circuit called top_cell which contain 2 other  sub-circuit A_cell and B_cell inside of A_cell and B_cell the power is vdd! and vss!. At the top_cell level A_cell need to connect to vddl_lvt an...
    last modified by nhumaile
  • [Questa] Migration from one PC to another -> Error:(vopt-7) -> still pointing to the "old" location -> how to fix?

    Hi All,   I moved my Questa project from one PC to another ...   While elaboration of the design, I'm receiving the following error message: ---------------------------------------------------------------...
    last modified by ldm.eth
  • How to create a high resolution image of a pyxis layout

    Is there a way to export or print a much larger resolution image of a pyxis layout. I want to frame the top level of a 4 bit computer I made but I am having trouble finding a way to getting a larger image of the layout.
    last modified by jahnjo
  • Issue with Quartus Prime Import in the HDL Designer Series 2018.2

    Hello! For some reasons, I am not able to import the Quartus Prime .qsys file to the HDL Designer. In attempts to find the cause, I tried a few various projects - from quite complex hierarchical ones to very simple w...
    last modified by igork
  • Via Override Under BGA's

    I need to reduce the plane between plane and via pad.... What's the tool to do this ??
    created by martinjaime