• [Questa] $MODEL_TECH -> where is defined? where should point?

    Hi All,   As for the $MODEL_TECH variable, where is it defined? Where should point to?   Thank you!
    last modified by ldm.eth
  • glbl + vcom/vopt/vsim libraries -> when used?

    Hi All,   1) What is the glbl library? What does it include and why needed?   2) What libraries should be loaded with the vsim command? Some libraries should be loaded/compiled with vcom, some of them with...
    created by ldm.eth
  • Layout not recognizing VDD and GND nets; LVS giving discrepancy errors

    Hello,   In Calibre's comparison results, I get four incorrect net discrepancies. Two are complaining that there are no similar nets for vdd and gnd in layout, and two are complaining that "Net 394" and "Net 398...
    last modified by dunn
  • 'Save Project' and 'Save Project As' TCL command

    Hi All,   Is there a Save Project or Save Project As TCL commands in Questa?   If I start a new project with the Questa GUI as 'File -> New -> Project' then there is no a problem - all the Project Se...
    last modified by ldm.eth
  • Error Messages -> is there a manual discribing ALL error messages?

    Hi All, Is there any database or manual, which describes all types of error messages (like vopt-7, vopt-1127, etc)? Thank you!
    last modified by ldm.eth
  • [Questa] Transcript window -> how to set different colors/fonts for the files and directories

    Hi All,   In the Transcript window, how to colorize the listed directories? files?   When I run the 'ls -la' command from the Transcript prompt, the files and directories are displayed with the same color ...
    last modified by ldm.eth
  • how to make lvs clean with different voltage domain ?

    Hi All, I have a circuit called top_cell which contain 2 other  sub-circuit A_cell and B_cell inside of A_cell and B_cell the power is vdd! and vss!. At the top_cell level A_cell need to connect to vddl_lvt an...
    last modified by nhumaile
  • [Questa] Migration from one PC to another -> Error:(vopt-7) -> still pointing to the "old" location -> how to fix?

    Hi All,   I moved my Questa project from one PC to another ...   While elaboration of the design, I'm receiving the following error message: ---------------------------------------------------------------...
    last modified by ldm.eth
  • How to create a high resolution image of a pyxis layout

    Is there a way to export or print a much larger resolution image of a pyxis layout. I want to frame the top level of a 4 bit computer I made but I am having trouble finding a way to getting a larger image of the layout.
    last modified by jahnjo
  • Issue with Quartus Prime Import in the HDL Designer Series 2018.2

    Hello! For some reasons, I am not able to import the Quartus Prime .qsys file to the HDL Designer. In attempts to find the cause, I tried a few various projects - from quite complex hierarchical ones to very simple w...
    last modified by igork
  • Via Override Under BGA's

    I need to reduce the plane between plane and via pad.... What's the tool to do this ??
    created by martinjaime
  • Create dynamic DRC run directory

    Hi,   I'd like to create a dynamic named DRC run directory when loading Calibre Interactive. For example, a run directory output folder with the following naming format:      <layoutviewn...
    last modified by rachel.spykerman
  • Understanding oasys warnings and TA messages

    Is there a document that describes the meaning of all Oasys warnings and a table listing what possible actions to take with respect to TA- messages? Also on the synthesis log, I see that oasys reports a lot of inform...
    last modified by schuler1
  • verilog hierarchy syntax

    Hi all,   Could you please tell how to describe the following hierarchy so that Questa can recognize?     I've used the hierarchy in do file:   tcheck_set ***.dfi_top_wrapper_U0/\RC_CG_HIER_INST...
    created by jol
  • Help with FATAL ERROR: Rules file must contain a CAPACITANCE ORDER statement

    In my current pdk, I do not have a CAPACITANCE ORDER statement in my rules file for CalibrexRC. Is there an example of this statement I can add to my rules file to enable a PEX verification run?   Currently usi...
    last modified by aguzman
  • periodic ac analysis in mentor design architect-ic

    Hi all,   I'm using mentor design architect v2008.2_7.1 to simulate a switched capacitive filter. As you know, I need to utilize periodic AC analysis rather than "normal" AC analysis. Even if there are some prov...
    last modified by e3402
  • ERROR(130): Incorrect MASK SVDB DIRECTORY options for this function.

    Hi All, I am doing a Calibre query using this command for QRC. calibre2017 -query /home/marben/GF55/GF_stuff/Components/cmos10lpe_CDS_oa_dl064_15_20170731/DRC_LVS_Run_Area/svdb pcd_inv_L -query_input query_cmd | tee...
    last modified by marben.orallo
  • Hierarchy LVS problem when using xcells to do hierarchical extraction

    Hi everyone,   I want to use hierarchical extraction for my design. I run LVS alone with hcells and it is right. But when I use the same hcells to run LVS in xRC, it turns out that my LVS is wrong. I set the hce...
    created by jiaqi
  • Error with Calibre PEX using IBM PDK

    Hello,   This is an update from my previous message in this community: https://communities.mentor.com/thread/22601   I am now using an updated version of Cadence (1.6.7.b where b = base version) and an up...
    last modified by growingmind
  • Questa formal - synchronizing signals

    hi i'm using Questa formal tool Version 10.7b_1. my question is: is there a way to force all signals to sync with the posedge of a clock (some "netlist" or anything else)?   thanks, Gidon 
    last modified by gid