• How to run a exe function from outside xpedition designer and write parameter into a component?

    Greetings, Could someone teach me how to run a EXE outside Xpediton designer or Layout , then to communicate with Xpedition Dxdesigner / Layout?  I would like to run a exe function which can generate some parame...
    tarence
    last modified by tarence
  • Error when simulating H2F AXI Bridge

    I am new to this and try to simulate a sample design of H2F AXI Bridge by following below link https://www.intel.com/content/www/us/en/programmable/support/support-resources/design-examples/design-software/qsys/exm-h...
    meow
    created by meow
  • DATABOOK ISSUE

    Hi there,   I faced USE OF PARAMETRIC DATA DISABLE error when ı had tried to open databook.    After this error, I shared an error message to CDT A.S. , that is authorized by MENTOR.    Thi...
    o_yardimci_600wy
    created by o_yardimci_600wy
  • PADs Layout Ground pour clearance setting issue.

    Hello ...!!   Currently we are facing some issue with PADs Layout / Router tool.    We have PCIe coplanar differential pair routing in Layer 3 and as per stack-up received from vendor, GND pour dista...
    prasadgokhale
    created by prasadgokhale
  • Automatic Ref-Des Arranger for Xpedition/PADS

    Hello again, As I stated while sharing Outline Assigner for Xpedition/PADS Professional and Bank Painter for Xpedition/PADS Professional, we have decided to open source some components of our PCB ...
    FUAT SENGUL
    last modified by FUAT SENGUL
  • Find Tool/Release of Multiboard Panel File

    Hello,   I'm working with a panel design file and I have to determine what software (Xpedition or PADS) (and its version) were used to create this PNL file. I do not have any PCB file related this pane...
    FUAT SENGUL
    created by FUAT SENGUL
  • No Snapshot error while opening Expedition PCB

    I was in the middle of an Expedition PCB layout when my computer decided to upgrade to OneDrive and reboot. Now, my .pcb project won't open and I get the following errors.        
    barneyhaugen
    created by barneyhaugen
  • Make Like Reuse Issue

    Hi All, In PADS Mentor graphics,following problems often occur during use, please help to see what the problem is and how to solve it, thank you!WARNING: Terminal position mismatch (Decal C0603, terminal #1) 0 r...
    ashok_007
    last modified by ashok_007
  • Display Control disappeared and is not displaying

    Good Day All..! I got an issue with my display control... I had a hipcup on Friday opening multiple boards and my display control disappeared and it's not displaying as it should. I believe it may be do...
    mthoma5
    last modified by mthoma5
  • How to run Batch Mode on signals with AC coupling capacitor in series?

    I am running into an issue where I have hundred to thousands of nets that have AC coupling capacitor in line with them. I can run them in linesim, sim it, and wait until the capacitor is charged. However, this would b...
    etrah808
    created by etrah808
  • Error while creating netlist (dxdesigner) with Reuse_block

    I am trying to generate a netlist with a reuse_block symbol (TOPLEVEL). And using this as symbol block in schematic1. I want to use Refdes prefix as S1, S2 (for two TOPLEVEL symbols). Also refdes inside S1 n...
    shafqat
    created by shafqat
  • Performance and "Enhancements"

    Hi all,   today I am frustrated again, because after updating the EDM library from VX2.3 to VX2.6 we get now a window to login to EDM each time when we open a design: opening a schematic: Login to EDM needed, o...
    deborah.frommer1
    created by deborah.frommer1
  • ECO to PCB very slow

    Is it normal that the ECO from sch to pcb or pcb to sch take 20 to 30 minutes?  why it takes so long?  is there a configuration setting that could speed up the process? I am using PADS LOGIC VX2.7  wit...
    rgomez
    created by rgomez
  • Error 329 in PCB layout and DxDesigner schematic comparison

    When I tried to compare the DxDesigner schematic with PADs layout, the system reports the error log file below:   viewbase: Error 329: Error - Duplicated port: VCC viewbase: Error 329: Error - Duplicated port: V...
    f_lu_clzcw
    created by f_lu_clzcw
  • Testers Wanted for PartQuest Beta

    Dear Customer,   Siemens invites you to test out a new PartQuest website at beta.partquest.com. The site look and feel remains the same as the current production partquest.com website, however, new back-end clo...
    caleigh_gold
    last modified by caleigh_gold
  • What is the purpose or functionality of VRM in Decoupling analysis in VX2.7?

    Hi All,    I noticed that in some archived on demand tutorials, there was no VRM setting in decoupling wizard. It looks like it's added in the decoupling wizard in VX2.7. Despite I know that VRMs work at ve...
    t_peng_4gngl
    created by t_peng_4gngl
  • How I can rename the existing project?

    Hello,    I want to change or modify the whole project name ( Schematic name and Layout design file name.  If I will modify both names manually then I get the error. How I can rename the existing pro...
    yasht
    last modified by yasht
  • Hyperlynx SI/PI via barrel plating thickness

    In Hyperlynx SI/PI, there is a global setting that specifies the via barrel plating thickness but this affects all padstacks.  Is it possible for Mentor to add functionality to allow the user to selectively modif...
    henryh
    last modified by henryh
  • add/delete symbol to Databook

    how to add my "local lib" schematic symbol to Databook standard library? VX 2.6 netlist flow. sorry guys we just lost our Librarian due to RIF, very basic question but I could not find anything at the forum.
    nalfaro
    last modified by nalfaro
  • Slow DDRx Batch Simulation

    Hi,   I'm working on the simulation of Post layout DDRx batch simulation in LineSim. But is very slow. I'm simulating with 1 driver and 4 memory devices (16bits). Is there any way to increase no of core or CPU i...
    asad_rehman
    last modified by asad_rehman