• Plating In PCB

    Hello Everyone,   I want to know the concept of plating in pcb aand what is its significance? while simulating through hyperlynx do we need to take care of Plating thickness while stac up editing.
    last modified by sandeep.kumar
  • EBD Question??

    I have a LineSim schematic setup with a LPDDR2 bus.  The DRAM has an IBIS model as well as an EBD file.  After running the simulation I have more probes than I expected?   DRAM1 is the reference design...
    last modified by kirk.fabbri
  • Getting errors while doing DDRx batch simulation read cycles

    Hi,   I am doing the DDRx batch simulations for DDR3 interface (DDR3 routing is completed and other interfaces routing is partially done)   I am not getting any issues while doing the data timing on write ...
    last modified by sk00101683
  • Hyperlynx analog simulation

    I am trying to simulate Worst-Case for Thermostat circuit. But .mod file of triac component found error ..\..\sym\triac_st.mod(92): error -- + is an unknow card. Could anybody tell me how to solve this error?
    last modified by victor1
  • Regarding to centre to centre distance of DC blocking caps of differential signals

    Please let me know if the centre to centre distance of DC blocking caps of differential signals is critical or not.   Many thanks.
    last modified by y.zhang
  • Accurate way to calculate timing margin using DDRx batch mode wizard

    Hi   I am using Hyperlynx 8.2.1 for DDR2 batch simulation.In order to calculate the timing margin by considering the flight time,test load has to be mentioned in ibis file.   The ibis files have test load ...
    last modified by kbmani
  • Frequency variable resistor

    Hi I want to add subck of wirewound coil according to model provided by manufacturer. Below model: http://www.coilcraft.com/pdf_viewer/showpdf.cfm?f=pdf_store:spice_0603cs.pdf   There is one frequency variable...
    last modified by michal.koziar
  • Gigabit ethernet with transformer

    Hello guys, can somebody recommend me some solution concerning the circuit with a gigait IC and transformer  to be able to simulate it? It is clear I have to have a simulation models - let's say I have only a (...
    last modified by MaBUa
  • Difference between results for HyperLynx and Eldo simulators...?

    Hi,   Conditions: SW/mode: HyperLynx SI LineSim circuit: a transmitter (IBIS), a piece of transmission line, a receiver (IBIS)   Please explain it to me, why I obtain a different results while running Hy...
    last modified by pjrajda
  • Via modeling - 3D

    Hi,   In hyperlynx 8.2.1, via modeling is possbile using 3D EM solver. It is allowed if the via is connected between two layers.   If I have a via with three ports ( one to the top, 2nd one to an inner l...
    last modified by kbmani
  • Help needed, Error throwing in boardsim: Too many drivers, not allowed in the DDR interface!

    Hi, I am trying for the DDR3 batch simulations, initially when I loaded the Hyp file and checking the 'audit simulation' for all the DDR signals i am getting the error "Too many drivers, not allowed in the DDR interf...
    last modified by sk00101683
  • XAUI simulation -help needed

    Hi,   I am using Hyperlynx SI tool V 8.2.1.   In XAUI simulation, AC coupling capacitor is kept near to receiver. Huge time is  required for the waveform to settle. I kept the time Scale: 500 ns / di...
    last modified by kbmani
  • HyperLynx connector via simulation

    Hi,   I have a backplane design loaded in BoardSim 8.2 and I want to extract the S-parameter of a differential signal path from connector to connector. The board has connectors press-fitted into via holes which...
    last modified by Jacques.A
  • S-Parameters/Spice netlist

    Hallo,   Could some one help me on how can I visualize *sp file which is extracted from Hyperlynx SI board sim? Also I have trouble in extracting S-Parameters file from Hyperlynx board sime. It gives an Error: "E...
    last modified by rpotluri
  • Not translating pads on vias and pins correctly from Allegro to boardsim

    Hi, When I use the via properties or visualizer in Hyperlynx boardsim, it still shows the pads on the layers unused/unconnected with the via or pin. I did remove those pads on unused layers in Allegro and I can see t...
    last modified by SiliconPhotonics
  • Co Simulation (Chip Die and Package and PCB board)

    Hello,   Is it possible to perform the co simulation ( Chip Die and Package and PCB board) with HyperLynx?   If not possible,  what if uisng s-parameters extracted from the package  and PC board?...
    last modified by bchoi
  • Plane noise analysis

    I have power track with one capacitor, one resistor(to fed voltage) and three load(IC pins). While doing a plane noise analysis for this net, I can not assign a model to capacitor throught the Plane Noise Analysus-&g...
    last modified by deepak.v.katkoria
  • eye mask for lvds

    hi   I need to simulate the LVDS singalling to check the signal qulaity. i want to create eye mask for LVDS. is there any default mask available?     Thanks Balajy
    last modified by balajy.kumar
  • Unable to select differential signals in boardsim

    I am trying to do post layout simulation for USB signals. When I try to select both D+/D- differential signals in the board file, only one gets selected. How do I select both????? The signals run from MCU to a PCIe ...
    last modified by hitheshn
  • Where put the probes on the FPGA : on PIN or DIE ??

    Hi.   I recently have to use Hyperlynx to estimate the delay between my FPGA and the DDR. For the simulation, i don't know what i have to choose for the location of the probes : "always at the pin" or "Always a...
    last modified by calimero_20039