• Linesim connector connection issue

    I am simulating differential signal that topology is IC to Connector. if i connect the termination resistor in output side the connection aero mark color showing  crisscrossing(in this issue impact on my oscillo...
    last modified by satheeshkumars
  • Hyperlynx batch/script?

    I have Hyperlynx VX2.6 and have a board with about 96 pairs of differential serdes I have one IBIS model for the transmitter and one for the receiver How can I batch test each pair of differential traces? Is there ...
    last modified by sspano01
  • Hypelynx LPDDR4 3733MT/s timing model

    I need to simulate a LPDDR4 at 3733 MT/s (Micron MT53D512M32D2DS-053) but I can't find the timing model in Hyperlynx, only 3200 or 4266 MT/s. Is there a solution? Thanks.
    last modified by lucbug
  • System Level PDN Impedance

    We have VRM spice model , PCB Model(S-parameter extracted from Distributed decoupling analysis, and package model(S-parameter format.) I dont know could we execute this in hyperlynx or not?Does hyperlynx support this...
    last modified by shravan.sk
  • How to stimulate a PDN with a CPM model?

    An IC vendor provide the CPM (chip power model) model and i am trying to carry on further investigation on a PDN's pcb board. The CPM looks like a Spice model with IPWL (current source) ports that should be attached ...
    last modified by oscar.martinelli
  • DDRx Batch-Simulation crashes when importing Setup File

    I setup a DDRx Batch-Mode Wizard and saved it as *.ddr file. When reopening the design i have to import the setup but it crashes without an error (Hyperlynx and Wizard a blured out white)   Do you know how to so...
    last modified by maddin
  • Variation of 90-ohms impedance across trace length

    Does TDR impedance has any relation with track length Below behavior is seen in 90ohms trace routed with constant trace width & separation, Please let me know if there is any reason for this behavior   T...
  • Batch Mode test DQS and DQS# fail when include Crosstalk effects in simulations.

    Hi guys, I'm trying to test a design with DDR3 memory through the DDRx Batch Mode Wizard but the test fail in DQS and DQS# when the Crosstalk effects are added to simulations. I'm modifying the ODT configura...
    last modified by eduardo_teo
  • Differential signal but different start time

    Recently I found my simulation on CLK/DQS have low Vix margin  from waveform i seen the CLK signal do not fall and rise at the same time and the time different about 60~90ps    the CLK/CLK# traces ar...
    last modified by alex_wong
  • DDRx Report: Getting an "N/A" and "Pass"

    I am getting an "N/A" and a "Pass" in the DDRx Report for the DQS signal (see attached). What does this mean and did it really pass? Could this point to an error on my pre-simulation setup?
    last modified by igby
  • Connector between PCB and RAM module

    Hi,  Recently I have a project about RAM module socket, place between DIMM PCB and ram module, how do I perform in Hyperlynx?   Do I need to make two board, 1 for raw card and 1 for module?   Or modi...
    last modified by alex_wong
  • USB data signal simulation Query

    Hi, I am simulating USB1 data signals in HyperLynx 2.4 using ibis model provided by ti. For USB1 data signals model is defined as NC in ibis model, so at the time of assigning model i cannot select it as output(refer&...
    last modified by jainika_kansara11
  • Differential Pair Skew Measurements

    Is there an easy way to measure the timing skew between the T/F lines in Hyperlynx? Is there a way to plot the average of the two signals so I can perform skew measurements?  I just want clarification so I know h...
    last modified by rjrodrig6
  • Hyperlynx DDRx vs Hyperlynx DRC

    Hello,   I'm not an experienced user of Hyperlynx tools. We are currently designing a board embedding a Xilinx Zynq MPSoC device interfacing 4 Micron DDR4 components. Xilinx provided us a Hyperlynx DRC timing r...
    last modified by sebo
  • Ibis AMI RX receiver output port eye diagram probe

    hi michel, I have a question to your Serdes expert and need an answer ASAP. see below: I am currently simulating the attached simple channel in hyperlynx with Xilinx GTY transiever RX and TX IBIS-AMI files @ 6.144Gbps...
    last modified by roi
  • Simulate DC Drop on Return Path in HyperLynx

    Hey, I'm using HyperLynx - BoardSim VX2.4. I'm currently doing post-route analysis on a particularly sensitive power form (core voltage for an SoC). I successfully ran a DC Drop simulation to get my drop from the out...
    last modified by jeffreymiller
  • Mentor Automating Design Compliance with Power-Aware Simulation HyperLynx and Xpedition Flow

    At Designcon, Todd Westerhoff, HyperLynx product manager, discussed how to reduce the high-speed analysis bottleneck by empowering engineers through automating design compliance with Power Aware Simulation. Read more ...
    created by caleigh_gold
  • Problem using SPICE simulation model of TI THS6052 in Hyperlynx Analog simulation

    Hello, PADS hyperlynx analog got an error when simulating THS6052 SPICE model at line ".MODEL Rtc RES TC1=-0.0055". The error is "..\..\sym\THS6052.mod(45): error -- res is an unknown model type." Any suggestion to ...
    last modified by nhd973
  • Add the DDR4 RCD timing model in the latest Hyperlynx release

    Dear Technical Supporter,   I am using Hyperlynx 9.4.2 but there is lack of the RCD timing model for DDR4 (ddr4_pllreg.v). I suggest to add this timing model to latest Hyperlynx version when it is released. ...
    last modified by hungreohd
  • Loading a file from Altium

    Hello;   I've been trying to load a file from Altium designer. On Altium I have created a .hyp file but when I open HyperLynx then File -> Open I don't see .hyp extension so I can't load my file.   Rgd...
    last modified by jdevettori