• Incorrect Voltage Levels DDR Batch Simulation

    Hello,   I'm noticing some discrepancies in voltage levels when I run DDR Batch Simulation vs. simulating a single data net on LineSim and wanted to know if I am running the batch simulation incorrectly. The DDR...
    mm784
    last modified by mm784
  • Assigning DDP DRAM

    Hi All,    I want to use a DDR4 Twin Die in simulation like "MT40A2G8NRE-083E". Micron have provide the IBIS on website, the file contain the IC and DDP package RLC      I want to ...
    alex_wong
    last modified by alex_wong
  • Hyperlynx DDR ODT Model Selector

    I am using hyperlynx for post route analysis on a DDR4 interface. I am trying to understand the ODT model selection for the controller and memory. I believe the ODT disabled column is for reads while the ODT enabled c...
    dcwang3
    last modified by dcwang3
  • Is it possible at BoardSim level to move stack-up layers?

    Hi, after a SERDES analysis I've seen that I might have a crosstalk problem related to adjacent layer nets. Is there a way to rearrange layers in order to perform again the SERDES compliance analysis with that stack-u...
    jjmoran
    last modified by jjmoran
  • Hyperlynx PDN settings

    We found the 5 settings below can influence PDN simulation result. 1. High-accuracy mode 2. Minimum void size 3. minimum metal-area size 4. defeature metal areas 5. defeature resolution Is there some recommendat...
    qqqqq
    created by qqqqq
  • How to add delay on DDR address / command when batch simulation

    How to add delay at address/cmd/Data/Strobe  when using the DDR batch Board sim simulation? I only see the write leveling sheet where i could add the delay on DQ/DQS. I would need to considerate the internal wi...
    okokjason
    last modified by okokjason
  • Need help for SERDES Batch Simulation

    Hi, I'm performing SERDES Batch Simulation to some nets of a board that are driven from a Mezzanine card to a Virtex FPGA. The problem is that I only have IBIS-AMI model of the FPGA, but I'm missing connector model a...
    jjmoran
    last modified by jjmoran
  • MAX SLEWRATE Failure

    Hi I am running the Hyperlynx DDR4 Wizard and on WRITE_FAST cycle, many signals fails due to SLEWRATE problem. I see values between -0.01 to -1.4 at the MAX-SLEWRATE column (see attached print-screen). When I selec...
    apomerants
    last modified by apomerants
  • Regarding differential traces assignments and differential model assignments 

    Hi ,   I am trying to perform a DDR3 batch simulation ,During this simulation do we need to assign differential nets for clock and DQS or in setup -->differential pairs or the DDR batch wizard while grouping ...
    agxinmj
    last modified by agxinmj
  • SAS 4.0 Spec S-Parameter Mask

    Hi, I am looking to analyze the IL and RL of multi-board system with SAS4.0 interface. How do I create mask in s-parameter file? Can the SAS4 spec mask be downloaded from any Mentor forum?   BR, Kumaran
    kumaran.balasubramanian
    last modified by kumaran.balasubramanian
  • Translation&Open Failure (Error Code 5.)

    Hi Team, I have trouble translating and opening one of the files created using Cadence 17.4 in Hyperlynx Boardsim VX2.7. Please note that other files created using Cadence 17.4 is successfully translated in same PC....
    kumaran.balasubramanian
    last modified by kumaran.balasubramanian
  • Linesim connector connection issue

    I am simulating differential signal that topology is IC to Connector. if i connect the termination resistor in output side the connection aero mark color showing  crisscrossing(in this issue impact on my oscillo...
    satheeshkumars
    last modified by satheeshkumars
  • Hyperlynx batch/script?

    I have Hyperlynx VX2.6 and have a board with about 96 pairs of differential serdes I have one IBIS model for the transmitter and one for the receiver How can I batch test each pair of differential traces? Is there ...
    sspano01
    last modified by sspano01
  • Hypelynx LPDDR4 3733MT/s timing model

    I need to simulate a LPDDR4 at 3733 MT/s (Micron MT53D512M32D2DS-053) but I can't find the timing model in Hyperlynx, only 3200 or 4266 MT/s. Is there a solution? Thanks.
    lucbug
    last modified by lucbug
  • System Level PDN Impedance

    We have VRM spice model , PCB Model(S-parameter extracted from Distributed decoupling analysis, and package model(S-parameter format.) I dont know could we execute this in hyperlynx or not?Does hyperlynx support this...
    shravan.sk
    last modified by shravan.sk
  • How to stimulate a PDN with a CPM model?

    An IC vendor provide the CPM (chip power model) model and i am trying to carry on further investigation on a PDN's pcb board. The CPM looks like a Spice model with IPWL (current source) ports that should be attached ...
    oscar.martinelli
    last modified by oscar.martinelli
  • DDRx Batch-Simulation crashes when importing Setup File

    I setup a DDRx Batch-Mode Wizard and saved it as *.ddr file. When reopening the design i have to import the setup but it crashes without an error (Hyperlynx and Wizard a blured out white)   Do you know how to so...
    maddin
    last modified by maddin
  • Variation of 90-ohms impedance across trace length

    Does TDR impedance has any relation with track length Below behavior is seen in 90ohms trace routed with constant trace width & separation, Please let me know if there is any reason for this behavior   T...
  • Batch Mode test DQS and DQS# fail when include Crosstalk effects in simulations.

    Hi guys, I'm trying to test a design with DDR3 memory through the DDRx Batch Mode Wizard but the test fail in DQS and DQS# when the Crosstalk effects are added to simulations. I'm modifying the ODT configura...
    eduardo_teo
    last modified by eduardo_teo
  • Differential signal but different start time

    Recently I found my simulation on CLK/DQS have low Vix margin  from waveform i seen the CLK signal do not fall and rise at the same time and the time different about 60~90ps    the CLK/CLK# traces ar...
    alex_wong
    last modified by alex_wong