• No convergence with DC assists

    how to resolve #convergence problems: There are some very #small-resistors which can cause non-convergence They are: X1I4594.R14 1.400000e-012 X1I4627.R14 1.400000e-012 X1I57.R1 4.200000e-010 REX1I103.Q1 1.00000...
    a_kumar_ok40u
    last modified by a_kumar_ok40u
  • Hyperlynx SI Attaching an S-parameter Connector with a Spice Mosfet

    I created a simple line sim model with a IBIS buffer attached to the Spice Mosfet and ran simulation and it works. If I introduce a S-parameter connector in its path the simulation fails. What is the criteria to attac...
    kharsyntiew
    last modified by kharsyntiew
  • Mapping mixed-mode s-parameter table to the actual parameters

    I'm working with a 12-port s-parameter model, which represents 3 differential channels. I've read a bit on the conversion to mixed-mode s-parameters for differential/common-mode analysis, and I understand how a 4-port...
    patrickyeor
    last modified by patrickyeor
  • Ports in full-wave solver

    Hi. Is there a simple way to create the ports with the correct size and reference in the full wave solver? If I import the design into hyperlynx and then export it to the full-wave solver I see that it aut...
    paoben
    last modified by paoben
  • Exporting and importing setups for Hyperlynx PI DC-IR drop

    I have a design that I setup all my VRM and sinks.  However, there is a change in the design and a new brd file is given to me.  How do I export all my VRM/sinks/R setups from the old hyp file to the new file?
    thoonky
    created by thoonky
  • Utilizing GPU in Hyperlynx Simulations

    May I know if Hyperlynx SW is actively looking at GPU on the systems and making use of them to solve the issues?  Or is there a setting that I can do to ensure the SW will use the GPU that we have on the system a...
    thoonky
    created by thoonky
  • 50ohm castellated hole

    Hi all. Is it possible to simulate a castellated hole in 3d simulator? I need to create a 50ohm castellated hole. Thanks.
    paoben
    last modified by paoben
  • LineSim vs. DDR Batch Simulation

    Hello   I am simulating DDR3 interface, and have tried comparing individual signals between the LineSim results (on scope) and DDR xBatch Simulation. For this I am using the same slew rate+strengt...
    mm784
    last modified by mm784
  • Simulating Data Write/Read

    After I simulated a Data WRITE and imported the resulting waveforms DQ (8 bits)and DQs into the digital oscilloscope, I am seeing expected waveforms, with appropriate leveling to make DQS out of phase with D...
    mm784
    last modified by mm784
  • Incorrect Voltage Levels DDR Batch Simulation

    Hello,   I'm noticing some discrepancies in voltage levels when I run DDR Batch Simulation vs. simulating a single data net on LineSim and wanted to know if I am running the batch simulation incorrectly. The DDR...
    mm784
    last modified by mm784
  • Assigning DDP DRAM

    Hi All,    I want to use a DDR4 Twin Die in simulation like "MT40A2G8NRE-083E". Micron have provide the IBIS on website, the file contain the IC and DDP package RLC      I want to ...
    alex_wong
    last modified by alex_wong
  • Hyperlynx DDR ODT Model Selector

    I am using hyperlynx for post route analysis on a DDR4 interface. I am trying to understand the ODT model selection for the controller and memory. I believe the ODT disabled column is for reads while the ODT enabled c...
    dcwang3
    last modified by dcwang3
  • Is it possible at BoardSim level to move stack-up layers?

    Hi, after a SERDES analysis I've seen that I might have a crosstalk problem related to adjacent layer nets. Is there a way to rearrange layers in order to perform again the SERDES compliance analysis with that stack-u...
    jjmoran
    last modified by jjmoran
  • Hyperlynx PDN settings

    We found the 5 settings below can influence PDN simulation result. 1. High-accuracy mode 2. Minimum void size 3. minimum metal-area size 4. defeature metal areas 5. defeature resolution Is there some recommendat...
    qqqqq
    created by qqqqq
  • How to add delay on DDR address / command when batch simulation

    How to add delay at address/cmd/Data/Strobe  when using the DDR batch Board sim simulation? I only see the write leveling sheet where i could add the delay on DQ/DQS. I would need to considerate the internal wi...
    okokjason
    last modified by okokjason
  • Need help for SERDES Batch Simulation

    Hi, I'm performing SERDES Batch Simulation to some nets of a board that are driven from a Mezzanine card to a Virtex FPGA. The problem is that I only have IBIS-AMI model of the FPGA, but I'm missing connector model a...
    jjmoran
    last modified by jjmoran
  • MAX SLEWRATE Failure

    Hi I am running the Hyperlynx DDR4 Wizard and on WRITE_FAST cycle, many signals fails due to SLEWRATE problem. I see values between -0.01 to -1.4 at the MAX-SLEWRATE column (see attached print-screen). When I selec...
    apomerants
    last modified by apomerants
  • Regarding differential traces assignments and differential model assignments 

    Hi ,   I am trying to perform a DDR3 batch simulation ,During this simulation do we need to assign differential nets for clock and DQS or in setup -->differential pairs or the DDR batch wizard while grouping ...
    agxinmj
    last modified by agxinmj
  • SAS 4.0 Spec S-Parameter Mask

    Hi, I am looking to analyze the IL and RL of multi-board system with SAS4.0 interface. How do I create mask in s-parameter file? Can the SAS4 spec mask be downloaded from any Mentor forum?   BR, Kumaran
    kumaran.balasubramanian
    last modified by kumaran.balasubramanian
  • Translation&Open Failure (Error Code 5.)

    Hi Team, I have trouble translating and opening one of the files created using Cadence 17.4 in Hyperlynx Boardsim VX2.7. Please note that other files created using Cadence 17.4 is successfully translated in same PC....
    kumaran.balasubramanian
    last modified by kumaran.balasubramanian