• Batch Mode test DQS and DQS# fail when include Crosstalk effects in simulations.

    Hi guys, I'm trying to test a design with DDR3 memory through the DDRx Batch Mode Wizard but the test fail in DQS and DQS# when the Crosstalk effects are added to simulations. I'm modifying the ODT configura...
    last modified by eduardo_teo
  • Differential signal but different start time

    Recently I found my simulation on CLK/DQS have low Vix margin  from waveform i seen the CLK signal do not fall and rise at the same time and the time different about 60~90ps    the CLK/CLK# traces ar...
    last modified by alex_wong
  • DDRx Report: Getting an "N/A" and "Pass"

    I am getting an "N/A" and a "Pass" in the DDRx Report for the DQS signal (see attached). What does this mean and did it really pass? Could this point to an error on my pre-simulation setup?
    last modified by igby
  • Connector between PCB and RAM module

    Hi,  Recently I have a project about RAM module socket, place between DIMM PCB and ram module, how do I perform in Hyperlynx?   Do I need to make two board, 1 for raw card and 1 for module?   Or modi...
    last modified by alex_wong
  • USB data signal simulation Query

    Hi, I am simulating USB1 data signals in HyperLynx 2.4 using ibis model provided by ti. For USB1 data signals model is defined as NC in ibis model, so at the time of assigning model i cannot select it as output(refer&...
    last modified by jainika_kansara11
  • Differential Pair Skew Measurements

    Is there an easy way to measure the timing skew between the T/F lines in Hyperlynx? Is there a way to plot the average of the two signals so I can perform skew measurements?  I just want clarification so I know h...
    last modified by rjrodrig6
  • Hyperlynx DDRx vs Hyperlynx DRC

    Hello,   I'm not an experienced user of Hyperlynx tools. We are currently designing a board embedding a Xilinx Zynq MPSoC device interfacing 4 Micron DDR4 components. Xilinx provided us a Hyperlynx DRC timing r...
    last modified by sebo
  • Ibis AMI RX receiver output port eye diagram probe

    hi michel, I have a question to your Serdes expert and need an answer ASAP. see below: I am currently simulating the attached simple channel in hyperlynx with Xilinx GTY transiever RX and TX IBIS-AMI files @ 6.144Gbps...
    last modified by roi
  • Simulate DC Drop on Return Path in HyperLynx

    Hey, I'm using HyperLynx - BoardSim VX2.4. I'm currently doing post-route analysis on a particularly sensitive power form (core voltage for an SoC). I successfully ran a DC Drop simulation to get my drop from the out...
    last modified by jeffreymiller
  • Mentor Automating Design Compliance with Power-Aware Simulation HyperLynx and Xpedition Flow

    At Designcon, Todd Westerhoff, HyperLynx product manager, discussed how to reduce the high-speed analysis bottleneck by empowering engineers through automating design compliance with Power Aware Simulation. Read more ...
    created by caleigh_gold
  • Problem using SPICE simulation model of TI THS6052 in Hyperlynx Analog simulation

    Hello, PADS hyperlynx analog got an error when simulating THS6052 SPICE model at line ".MODEL Rtc RES TC1=-0.0055". The error is "..\..\sym\THS6052.mod(45): error -- res is an unknown model type." Any suggestion to ...
    last modified by nhd973
  • Add the DDR4 RCD timing model in the latest Hyperlynx release

    Dear Technical Supporter,   I am using Hyperlynx 9.4.2 but there is lack of the RCD timing model for DDR4 (ddr4_pllreg.v). I suggest to add this timing model to latest Hyperlynx version when it is released. ...
    last modified by hungreohd
  • Loading a file from Altium

    Hello;   I've been trying to load a file from Altium designer. On Altium I have created a .hyp file but when I open HyperLynx then File -> Open I don't see .hyp extension so I can't load my file.   Rgd...
    last modified by jdevettori
  • hyperlynx si/pi python examples

    I see python was added somewhere between 9.4 and VX2.4 release.   I currently have VX2.4 installed. I don't see any information about using python when I launch help documentation. Are there any example applicat...
    created by jasonluu
  • Current density on the vias - Vdrop simulation

    Hi, I'm exporting the design from Altium to Hyperlynx to doing Vdrop simulation. I'm not sure of results when I see the vias current density distribution. I don't find the thickness of vias wall settings (hole coppe...
    last modified by ruscino
  • Netlisting errors

    I have been following this video tutorial found here. HyperLynx Analog: Simple RC Design (2) - YouTube   However I get the following errors when I try to generate the net list.   *Warning: No Value For CD...
    created by robertpetersen
  • Hyperlynx SI with "Beads In Trace"

    Hi,   I'm currently doing SI analysis of a SERDES link for one of our customers. He has placed "beads-in-trace" on these lines.   These things are soldermask openings, with some solder on them, so they ...
    last modified by tim_baestaens
  • HyperLynx: HTML report creation failed

    Hi all, I use Hyperlynx for simulate DDR3, using DDRwizard. When simulation is finished, there is a message:   [INFO]Generating HTML report... [INFO]Traceback (most recent call last): [INFO]  File "C:\Me...
    last modified by tuongpv
  • Hyperlynx VX.2.3 AC couple caps 3D model extraction

    Hello,   I have found some similar topics, but none give me the answer I'm looking for, nor any of the help files... Well, I want to simulate a SERDES link, routed completely on TOP, but with AC couple caps. T...
    last modified by tim_baestaens
  • SerDes Wizard (VX.2.3)

    Hello,   I have been SerDes Wizard to test a diff pair.   Bellow is a list of steps:   1. Open a board file 2. Defined a pair under test as a diff pair using the "differential Pair" tab 3. Starte...