• hyperlynx si/pi python examples

    I see python was added somewhere between 9.4 and VX2.4 release.   I currently have VX2.4 installed. I don't see any information about using python when I launch help documentation. Are there any example applicat...
    jasonluu
    created by jasonluu
  • Current density on the vias - Vdrop simulation

    Hi, I'm exporting the design from Altium to Hyperlynx to doing Vdrop simulation. I'm not sure of results when I see the vias current density distribution. I don't find the thickness of vias wall settings (hole coppe...
    ruscino
    last modified by ruscino
  • Netlisting errors

    I have been following this video tutorial found here. HyperLynx Analog: Simple RC Design (2) - YouTube   However I get the following errors when I try to generate the net list.   *Warning: No Value For CD...
    robertpetersen
    created by robertpetersen
  • Hyperlynx SI with "Beads In Trace"

    Hi,   I'm currently doing SI analysis of a SERDES link for one of our customers. He has placed "beads-in-trace" on these lines.   These things are soldermask openings, with some solder on them, so they ...
    tim_baestaens
    last modified by tim_baestaens
  • HyperLynx: HTML report creation failed

    Hi all, I use Hyperlynx for simulate DDR3, using DDRwizard. When simulation is finished, there is a message:   [INFO]Generating HTML report... [INFO]Traceback (most recent call last): [INFO]  File "C:\Me...
    tuongpv
    last modified by tuongpv
  • Hyperlynx VX.2.3 AC couple caps 3D model extraction

    Hello,   I have found some similar topics, but none give me the answer I'm looking for, nor any of the help files... Well, I want to simulate a SERDES link, routed completely on TOP, but with AC couple caps. T...
    tim_baestaens
    last modified by tim_baestaens
  • SerDes Wizard (VX.2.3)

    Hello,   I have been SerDes Wizard to test a diff pair.   Bellow is a list of steps:   1. Open a board file 2. Defined a pair under test as a diff pair using the "differential Pair" tab 3. Starte...
  • IBIS-AMI

    Hello,   I have been running an IBIS-AMI based project. There have been no problem to simulate the project. My question is , how to save the data generated in  the report. I don't see any log files generat...
  • Hyperlynx SI Generic IBIS Models

    Does Mentor Graphics provide generic driver and receiver buffer models that just follows an IOSTANDARD (e.g. TIA/EIA-644-A (LVDS))? I just want to use a driver and receiver buffer and not search for a driver from a pa...
    slade392
    last modified by slade392
  • DDR Wizard's TM clock!

    Hi, I am trying to run DDR3 batch simulation on Hyperlynx. While making my timing model in the timing wizard, i see in the timing diagrams that the clock is single ended. Why is that so? Shouldn't the clock in DDR3 b...
    qammarabbas313@gmail.com
    last modified by qammarabbas313@gmail.com
  • FPGAs Package Capacitor Consideration during PI Analysis

    HI I am trying to use Hyperlynx PI (ver. 9.2) to do decoupling analysis for Xilinx-Kintex7 fpgas. The user guides of these FPGAs explicitly mention that these FPGAs have enough on-package decoupling capacitors that w...
    chandan_eldaas
    last modified by chandan_eldaas
  • Hyperlynx DDR Wizard Pin Mapping

    Hi, I am trying to run DDR3 batch simulation on Hyperlynx. I have assigned the ibis models to the controller and the DRAM (please find attached image), however when i do automatic net mapping the pins/nets of the con...
    qammarabbas313@gmail.com
    last modified by qammarabbas313@gmail.com
  • DDR Batch wizard monotonicity

    Hi,   I'm running some DDR4 analysis and I have some DDR Writes which are failing the monotonic test. When I examine the waveform I see the following:     One thought as to why this is might be fa...
    pjs
    last modified by pjs
  • DDR Batch wizard - inconsistent ignored transistions

    I'm using the DDR Batch wizard to analyse a DDR4 bus. I have a failing tDQSS measurement which is failing by a substantial amount compared to the other DQS in the system.     Whilst there are a couple of ...
    pjs
    last modified by pjs
  • Showing Thresholds for IC's Models  in  EZwave

    Hello,   Is there a way to configure EZWay to show thresholds of IC's Models the same way as they shown in the Oscilloscope viewer. I have attached a snippet below     Regards,   Alex
  • Eye diagram before + after rx equalisation

    I'm trying to examine the eye diagram of a signal before and after the rx equalisation. The main reason is to ensure that  we meet the minimum eye opening at the receive pins as specified in the datasheet. This i...
    pjs
    last modified by pjs
  • Digital Oscilloscope with IBIS-AMI

    Am I right in thinking the Digital Oscilloscope does not use the full algorithmic part of the IBIS-AMI model and it just uses the I-V analogue model in the IBIS file?   If so, I'm not sure I understand how repre...
    pjs
    last modified by pjs
  • Segment Skew

    In HyperLynx BoardSim, is there a way to select segments of a net and measure length/delay of just the selected segments? I only appear to be able to select the whole net and see the overall net length.   I'm tr...
    pjs
    last modified by pjs
  • Virus S/W & Hyperlynx?

    It has been a few months since I have installed an update for PADS, I didn't get any warnings, but have now noticed two files in my quarantine using VIPRE Endpoint Security. The are; crd2hyp.exe    &...
    wolferm
    last modified by wolferm
  • Some doubts about Hyperlynx:Altium designer to hyperlynx queation!Asking for help!Thanks!!!

    Dear all!!! I want to use this program to similate a DC boost circuit.Its shematic is shown below: I draw this circuit in Altium Designer. I use this program to export .hyp document for Hyperlynx. The circuit in Hype...
    gloria2018
    last modified by gloria2018