Log in to follow, share, and participate in this community. Hi All, i am running a Soldermask Clearance Check and i get unexpected results. According to this text it is checking between soldermask edges. I have setup the parameters... Hi, I want to run the rule "Delay and Length Matching". Each net in the group of nets i want to use, splits in the middle of the trace by a via. I want to define new nets, end to end, maybe by the components pin... Where can I download the free version of HyperLynx DRC? I recently downloaded a version of the software but I only had a 30 day trial and it has recently run out. How do I request an activation key for HyperLynx DRC Free edition? If I search the communities it says 'look in your activation email', well I never got one. There's no 'activation license' on my account center and ... Hi all, I am beginning to use HyperLynx DRC and I am stuck with this question. There is a net (X) that has a series capacitor and so the same net section after the cap is named as (X_C) and my question here is... Hello, During violation review if I go to Action ->Zoom to Violation and I got message "You'll need a new app to open this about" I am working with W10., HyperLynx DRC 6.2.3 (64bit). How can I ... After importing an Allegro.brd file into HyperLynx DRC, the Radiation High Electrical Net is loaded with signal nets. Some of the listed nets are board straps and would not be considered Radiation High. How do I edit ... I have a 6 layer design where I want to check nets crossing plane gaps. But, I only want to check against certain layers. Specifically layer 1 and 2 where layer 1 is signal layer and layer 2 is split PWR/G... When running rules on the entire design, the impedance checking for single-ended signals seems to understand that it should ignore net classes like power and ground (constant nets). However it incorrectly checks... I want to check Net crossing gap rule. I have the next stuck up configuration: When i run this rule i have the next vialation: Why HyperLynx DRC define signal_10 as reference layer? Correct reference layer mus... How does Hyperlynx DRC identify a reference layer for a trace & how we can change reference layer for a trace manually. PS: see attached file for reference Hi all I try to use in my automation script (VBS) in HL DRC Layer properties and I receive error Microsoft VBScript runtime error: Object doesn't support this property or method Mytrace.Name I can read w... Hi, On a DDR4 interface we are trying to do delay matching in layout (VX 2.4). This is done using CES, however CES is giving us violations which we don't really have a clue yet on why we get these violations. ... Hi, Good day I am initial stage in HLDRC, So i ask the question some time is . o k .,,, come to the point I am allegro user I have the board file, when i import .brd file its automatically take constraint m... Hi , Good day When i start verify the Design i couldn't find capacitor value? Plz Some one help. Thanks, Mareeswaran K The latest version of the HyperLynx DRC Frequently Asked Questions (FAQ) includes new questions and answers and is organized by topic to make it easier to find what you're looking for. Click 'View' or 'Download' to ac... New in HyperLynx DRC VX.2.4: automated high-voltage creepage checks that eliminate the tedious work associated with PCB validation and make it easy to find design errors. Watch now! We have lots of materials to help you learn and use HyperLynx electrical design rule checks: Knowledge Base (KB) article - includes tips for getting started and 20+ videos! HyperLynx DRC FAQ - newly updated for Hype... HyperLynx DRC has LtoW Ratio (rule- Metal Island, Long Stub) This value defaults to 10. If this value is 0.49, it will be checked as 10 which is the default value. WARNING: using default value for the LtoWRatio ... I imported an odb file into hyperlynx and ran EMI simulation. The drill hole has no copper but not sure what is happening and need some help with this?