• HyperLynx DRC: Define a net by components pins

    Hi, I want to run the rule "Delay and Length Matching". Each net in the group of nets i want to use, splits in the middle of the trace by a via. I want to define new nets, end to end, maybe by the components pin...
    lior
    last modified by lior
  • HyperLynx DRC Free Version

    Where can I download the free version of HyperLynx DRC? I recently downloaded a version of the software but I only had a 30 day trial and it has recently run out. 
    m_rabe_m1l8p
    last modified by m_rabe_m1l8p
  • HyperLynx DRC Free activation email?

    How do I request an activation key for HyperLynx DRC Free edition? If I search the communities it says 'look in your activation email', well I never got one. There's no 'activation license' on my account center and ...
    gbox
    last modified by gbox
  • HyperLynx DRC: How to associate two nets together separated by a series cap?

    Hi all,   I am beginning to use HyperLynx DRC and I am stuck with this question. There is a net (X) that has a series capacitor and so the same net section after the cap is named as (X_C) and my question here is...
    l_karunanithi_rl2zy
    last modified by l_karunanithi_rl2zy
  • You'll need a new app to open

    Hello, During violation review if I go to Action ->Zoom to Violation and  I got message "You'll need a new app to open this about"  I am working  with W10., HyperLynx DRC 6.2.3 (64bit). How can I ...
    vladimir.karalnik
    last modified by vladimir.karalnik
  • How do you delete or add a signal to the Radiation High Electrical Net

    After importing an Allegro.brd file into HyperLynx DRC, the Radiation High Electrical Net is loaded with signal nets. Some of the listed nets are board straps and would not be considered Radiation High. How do I edit ...
    pfwynhamer
    last modified by pfwynhamer
  • How to check nets crossing gaps for specific layers

    I have a 6 layer design where I want to check nets crossing plane gaps.  But, I only want to check against certain layers.  Specifically layer 1 and 2 where layer 1 is signal layer and layer 2 is split PWR/G...
    marty_fouch
    last modified by marty_fouch
  • How do I prevent differential pairs from being checked for single-ended impedance in Hyperlynx DRC

    When running rules on the entire design, the impedance checking for single-ended signals seems to understand that it should ignore net classes like power and ground (constant nets).  However it incorrectly checks...
    gaborsz
    last modified by gaborsz
  • Changing CoeffAccountable parametr does not affect on results

    I want to check Net crossing gap rule. I have the next stuck up configuration: When i run this rule i have the next vialation: Why HyperLynx DRC define signal_10 as reference layer? Correct reference layer mus...
    pbo
    last modified by pbo
  • How we can change reference layer for a trace ?

    How does Hyperlynx DRC identify a reference layer for a trace & how we can change reference layer for a trace manually. PS: see attached file for reference
    kartik_
    last modified by kartik_
  • Problem with Trace.Layer properties

    Hi all   I try to use in my automation script (VBS) in HL DRC Layer properties and I receive error Microsoft VBScript runtime error: Object doesn't support this property or method Mytrace.Name  I can read w...
    strdaniel@o2.pl
    last modified by strdaniel@o2.pl
  • Pin package length and delay

    Hi,   On a DDR4 interface we are trying to do delay matching in layout (VX 2.4). This is done using CES, however CES is giving us violations which we don't really have a clue yet on why we get these violations. ...
    jakob
    last modified by jakob
  • CMGR need to import separately

    Hi, Good day   I am initial stage in HLDRC, So i ask the question some time is . o k .,,, come to the point I am allegro user I have the board file, when i import .brd file its automatically take constraint m...
    mareeswaran_karuppiah
    last modified by mareeswaran_karuppiah
  • Capacitor Value - HLDRC

    Hi , Good day   When i start verify the Design i couldn't find capacitor value? Plz Some one help.   Thanks, Mareeswaran K
    mareeswaran_karuppiah
    last modified by mareeswaran_karuppiah
  • HL_DRC_FAQ_Sept2018_by-topic.docx

    The latest version of the HyperLynx DRC Frequently Asked Questions (FAQ) includes new questions and answers and is organized by topic to make it easier to find what you're looking for. Click 'View' or 'Download' to ac...
    cathy_terwedow
    last modified by cathy_terwedow
  • Multi-layer safety clearance and creepage rules

    New in HyperLynx DRC VX.2.4: automated high-voltage creepage checks that eliminate the tedious work associated with PCB validation and make it easy to find design errors. Watch now!
    cathy_terwedow
    last modified by cathy_terwedow
  • Need help getting started with HyperLynx DRC?

    We have lots of materials to help you learn and use HyperLynx electrical design rule checks: Knowledge Base (KB) article - includes tips for getting started and 20+ videos! HyperLynx DRC FAQ - newly updated for Hype...
    cathy_terwedow
    last modified by cathy_terwedow
  • LtoW Ratio 0.5 & 0.49

    HyperLynx DRC has LtoW Ratio (rule- Metal Island, Long Stub) This value defaults to 10. If this value is 0.49, it will be checked as 10 which is the default value. WARNING: using default value for the LtoWRatio ...
    ksh
    last modified by ksh
  • Drill hole on the pcb shows as a metal island error?

    I imported an odb file into hyperlynx and ran EMI simulation. The drill hole has no copper but not sure what is happening and need some help with this?
    sripriya@codecorp.com
    last modified by sripriya@codecorp.com
  • Is HyperLynxDRC Impedance calculation accurate?

    Hi, Can anyone suggest if HyperLynx DRC impedance calculations are correct enough to use as regular DRC check? There is very minimal settings in the layer stackup and missing critical information. When I ran impedan...
    rshrestha84
    last modified by rshrestha84