• DDRx, considering package deskew

    Also check the probe location, DDRx batch simulation probably uses the die as probe location while the default setting in the scope is 'always at pin'
    matthias.cosaert
    last modified by matthias.cosaert
  • Encrypted spice model

    I have an encrypted model of an LED in .sp format. I tried to assign it but it gives an error that "The selected library is unusable. Please select a different library". Does anyone have an idea how it can be assigned...
    sms
    last modified by sms
  • Parametric Sweep

    The Sweep manager dialog box does not list passive components, transmission lines, coupling regions in the design property tree as shown in the Hyperlynx SI User guide. Am I missing something, somewhere? Would appreci...
    sms
    last modified by sms
  • Please provide topics you want to see for future HyperLynx webinars

    Hello all, HyperLynx support team has been delivering webinars and short videos beginning in 2016 to help the users get up to speed quickly and be successful with HyperLynx SI/PI/DDRx/DRC. Please see the future and...
    min_maung
    created by min_maung
  • How to use encrypted spice model in Hyperlynx 8.0

       I got the encrypted spice model (.inc file)  which can't be read/edit by wordpad or other text editor but can be used in Hspice. So how to use this encrypted spice model in Hyperlynx 8.0?
    bruce_qin
    last modified by bruce_qin
  • HyperLynx and IBIS AMI with Xilinx webcast is on-demand

    If you missed it, the HyperLynx IBIS AMI webinar with Xilinx that was yesterday (1/28) is now available on-demand.  You can check it out here:   http://www.mentor.com/products/pcb-system-design/multimedia/m...
    Steve_McKinney
    last modified by Steve_McKinney
  • High speed Multiboard design using Boardsim

    Hi,   I have used 'linesim' before for evaluating PCIe and other devices using respective IBIS models. However, for our new project, we have a system where say 'Board 1' has a SOC controller on it and a differet...
    sandeep.dattaprasad
    last modified by sandeep.dattaprasad
  • SI/PI simulation only with passive components

    Hi,   I am a learner of Hyperlynx SI/PI. I am confused about one question. If I have a board without any ICs and only have some passive components like resistors and capacitors on it, can I still set up the powe...
    yihong.yang
    last modified by yihong.yang
  • Looking for Hyperlynx - Signal Integrity Experts

    I am looking for engineers skilled in using Hyperlynx to do Signal integrity analysis.   We are an analysis services company specializing in doing Analog and Digital Worst Case Circuit Analysis for Hi-Rel system...
    charles2
    last modified by charles2
  • Terminator wizard question

    I am trying to determine the output impedance of a buffer using the run terminator wizard. The expected answer is 150 ohm. But the terminator says it's 50 ohms. See attachment.   Assuming output impedance is 150...
    hithesh.n
    last modified by hithesh.n
  • how to get demonstration enable code for hyperlynx ?

    Hi  everyone i am new bie for hyperlynx. i need to enable the demonstration enable code for hyperlynx how to enable ?? for whom i need to contact ??please reply anyone
    kabaleeswaran.K.R
    last modified by kabaleeswaran.K.R
  • Stack up issue

    Hi Everyone,   Can some one tell me regarding the differences between folllowing while editing stack up:   Thickness(um), Test Width(um), Z0 Ohm & Target Z0 ohm.   Kindly explain the difference....
    sandeep.kumar
    last modified by sandeep.kumar
  • ?      ** Warning(Severe) ** Could not analyze SI; DC operating points not valid; check model thresholds

    Hi,   I am analysing one PCB with Generic Batch Simulation with hyperlynx. I assaigned the SDRAM & Controller pins with IBIS models. Addredd lines Batch simulation was done correctly. While doding the same p...
    bhagyamala.sunku1
    last modified by bhagyamala.sunku1
  • How to use S-parameter package model of the controller device in a DDRx batch simulation

    I am running a DDR3-1600 post-layout batch simulation using a DIMM connector. I have implemented connector model. I have problem implementing package model. I got ibis model and package model in separate files for the...
    s.roy
    last modified by s.roy
  • Export  LineSim schematics from DxDesigner

    Hello everybody,   I'm starting to learn how to use HyperLynx so I have some questions:   1) I have done some schematics with DxDesigner, how can I export them on Hyperlynx?      ...
    marco.di_vivo
    last modified by marco.di_vivo
  • Eye Mask Values

    Hello Everybody,   In Eye mask settings what are the values of voltges we have to feed in that diagram for DDR-3? Is it Vih,Voh or some other values? I want to do it for DDR3 address & Data signals kindly t...
    sandeep.kumar
    last modified by sandeep.kumar
  • How to run hundreds of HyperLynx .ffs files automatically?

    I created hundreds of .ffs and .pjh files based on IBIS models; i.e. one pair for each IO standard. I can then load the .ffs file in HyperLynx using batch file. Does HyperLynx have commands or scripts capability allow...
    ching-chia.tien
    last modified by ching-chia.tien
  • Startup of Hyperlynx

    L.S.   How to prevent (EE7.9) Checking out (trying) of NOT selected features of Hyperlynx V8.1. This is a problem with sites having already a latency problem, because of this behavior starting up takes additional...
    peter.quadflieg
    last modified by peter.quadflieg
  • Can Hyperlynx PI DC Have A Feature like Flo.therm's Bottleneck and Shortcut?

    Hi Steve,   Flotherm's Bts and Scs are  helpful to designer, they can get know how and in where to improve the design. is It possible that Hyperlynx learn this concept and implement a similar feature to hel...
    yu.yanfeng
    last modified by yu.yanfeng
  • Hyperlynx Eval. download

    Is it possible to get an evaluation copy of Hyperlynx? Thanks.
    RG
    last modified by RG