• C-comp and output risetime

    We have discovered that with Hyperlynx 8.0 the output rising edge is dependent on the value of c_comp. From what I understand this is wrong. We are modeling an Altera Arria IIGX part (LVDS) and if we set c_comp = 0pf...
    david.royle
    last modified by david.royle
  • Advanced Decoupling Error

    Hello Experts, I am running Advanced Decoupling Analalyis, am getting a below error. Please let me know how can i resolve it? regards, SK.   Error:-   I: 01/10, 21:14:34] [INFO] Checking In License Fea...
    shravan.sk
    last modified by shravan.sk
  • DC Resistance /RLGC

    Hello Experts, Can we extract DC Resistance/RLGC of Power planes in hyper-lynx? Please do the needful. Regards, SK
    shravan.sk
    last modified by shravan.sk
  • DDR3 Setup and Hold Time Calculations

    Sir I am doing DDR3x Batch Simulations using hyperlynx. Upon completion of the simulations, it gives result pass and fail results and outputs an excel sheet. When I click setup tab, It expands and open up 5 columns....
    m.ather
    last modified by m.ather
  • HyperLynx V2.4 SERDES wizard supported protocols

    Hi,       I am trying to use the SERDES wizard of HyperLynx V2.4 to analyze a SATA bus. It does not seem to have SATA listed in the "Protocol" list. Is there a way i can add it to the list? Is there a ...
    narasimhamurthy
    last modified by narasimhamurthy
  • With respect to HyperLynx SI/PI, what is the difference between .hyp and .cce files? Is one better than the other?

    hyperlynxsignalintegrity For Signal Integrity simulations which one is better *.cce or *.hyp? Which file is better for sharing information?
    narasimhamurthy
    last modified by narasimhamurthy
  • EBD file assignment/usage Boardsim V2.3_Update 1

    First time user of EBD files and admittedly a while since I used Hyperlynx. The DDR model I'm using was provided from a supplier in a zip. I imported a .CCE file into a NEW Board simulation since the DDRx ar...
    james_stafford
    last modified by james_stafford
  • Need Help for ddr3 simulation at 1600 MT/s (ddr3_ctl.v)

    Hi! I am designing a custom board with T1042 processor and adding DDR3 memory with it. Now at PCB stage i need to do some simulations to see if my RAM is routed well or not. i have successfully simulated it on 1333MHZ...
    m.ather
    last modified by m.ather
  • HyperLynx Thermal

    Why does HyperLynx Thermal does not take negative Temperatures? When I try to enter a negative number (-40 for example), the GUI records 0 instead. If this is a bug on the GUI, please address it because the automoti...
    c_nzeyimana
    last modified by c_nzeyimana
  • Sense Connection

    Hello Experts,   Can we simulate DC drop considering effect of voltage sense connection in hyperlynx?   Regards, SK .
    shravan.sk
    last modified by shravan.sk
  • IBIS-AMI MODEL ASSIGNMENT

    DURING IBIS-AMI CHANNEL ANALYSIS  .ami AND .dll ASSIGNMENTS I AM RECEIVING AN ERROR THAT "YOUR DLL REQUIRES AN ANOTHER .DLL THAT IS NOT PRESENT " KINDLY GUIDE REGARDS#
    engr.adam76@gmail.com
    last modified by engr.adam76@gmail.com
  • EMI/EMC/Antenna Simulation

    Hello Team,   Can we perform EMI/EMC and Antenna Simulation in Hyperlynx advanced solver?   If yes,Please guide me to simulate.   Regards, SK
    shravan.sk
    last modified by shravan.sk
  • Hyperlynx : DRR3 Batch Simulation Data Read Problem

    We are simulation DDR3L in our design and we are trying to simulate our chips through Hyperlynx DDR3 batch simulation. We have used one slot dual ranked settings. After setting the parameters required for DDR3 batch s...
    m.ather
    last modified by m.ather
  • Digital Oscilloscope maximum oscillator frequency

    HI, I have a SDI 12 GHZ to simulate, can i setup the Oscillator frequency at 12000 Mhz ? Thanks
    stephane
    last modified by stephane
  • Does HyperLynx take via stubs into account? If so, how?

    I'm running an HL simulation (HyperLynx SI/PI/Thermal VX.2.4_Update 1) of a PCIe Gen 2 link running across a VPX backplane. It does not seem to take the via stubs into account, and I want to know if I'm doing somethin...
    daleb777
    last modified by daleb777
  • Ground Vs. Power Planes & Impedance

    I note that Hyperlynx LineSim does  not differentiate between power and ground planes in a layer stackup.   Does this mean there is no difference between power and ground planes  when defining a co...
    dupre
    last modified by dupre
  • Hyper lynx DDRX Batch Simulation V 2.4

    Hello, I'm running DDR4  DDRX Batch Simulation. Designed as been failed because of VAC/DC threshold.  Could Any one help us to solve the problem.
    chandraprakash
    last modified by chandraprakash
  • Via Modeling

    Hi,  I want to do via modeling in Hyperlynx Full Wave Solver VX2.3 for 20 layer board.  Here we have 2 kind of Layer transition on via as L1 to L16 and L1 to L18 for same via structure.  Should I do ...
    sivasankars
    last modified by sivasankars
  • Board level thermal

    we wan to add polymide laminate that has low CTE.How to embed low CTE value and perform board level thermal analysis.
    rj&j
    created by rj&j
  • Quarter wavelength rule?

          I know something about the mysterious quarter wavelength rule, it is usually to be said as: when routing high speed signal trace, the trace length must be avoided to become integral mult...
    bruce_qin
    last modified by bruce_qin