• AC Decoupling Analysis with Interdigitated Capacitor

    Anyone have success modeling an interdigitated capacitor in Hyperlynx Decoupling Analysis? It's a single capacitor with 8 pins to lower ESL.    I looked at assigning a PAK but none of the three options (ser...
    user987654321
    last modified by user987654321
  • VIX MARGIN

    RUNNING THE DDR3 SIMULATION, IN THIS SIMULATION THE CLOCK SIGNAL GETTING FAILED BECAUSE OF VIX MARGIN, CAN ANY ONE TELL ME WHY ITS GETTING FAILED/SUGGEST THE SOLUTION . MY OPERATING FREQUENCY IS 400MHZ, & IAM USIN...
    ecs
    last modified by ecs
  • Xilinx FPGA and DDR4 simulation is not working, Vih and Vil levels is not meeting desired range.

    Hi All,   I am doing the simulation for the xilinx FPGA and DDR4 interface. I have a proper eye opening but its referenced to 0V. The Eye starts from 0V to 0.6V, with the crossing point 0.3V. Any changes on driv...
    ashwin9754
    last modified by ashwin9754
  • IBIS-AMI Eye Diagram

    Hi, I use the IBIS-AMI analyzer for 28GbNRZ waveform and here is what I got from  SweepViewer with 1milbit      Here is the eye with Digital Oscilloscope with 2^15   How I can fix the e...
    t_hoang_m0mka
    last modified by t_hoang_m0mka
  • "EZwave is not available" in hyperlinx

    I am unable now to run my simulations in Hyperlynx because of this error.   I've tried uninstall and reinstall as well as countless restarts. This is occuring after a windows 10 update on my machine which may b...
    jrenfro
    last modified by jrenfro
  • Printing Hyperlynx Thermal results?

    I just started exploring Hyperlynx Thermal from PADS Professional. Not quite intuitive to edit working library to assign power to parts, but it's a nice tool.   However, how do I publish the result? As it is n...
    gbox
    created by gbox
  • What is export coupled segments

    While exporting to free form schematic, there is an option for export coupled segments. What is the use of this option??.. What happens if that option remains deselected and proceed further?
    sujin
    last modified by sujin
  • Trace width of Differential nets should be the same as single-ended trace?

    In the StackUP editor of HyperLynx or Xpedition Layout tools, Should I need to have the Trace width of Differential nets should be the same as a single-ended trace for the same layer? Please see attached image for ...
    kartik_
    last modified by kartik_
  • What is the best method for working with an Altium to Hyperlynx setup?

    We are working with a customer that wants to use Hyperlynx for Simulation after completing their design in Altium.  It seems that Altium does not export Part names or values hence all R's & C's values are w...
    brian1
    last modified by brian1
  • Decoupling analysis with inductors

    Good afternoon,   I have seen this topic mentioned before but I really wanted to have a full picture. Is it possible to include an inductor in your decoupling analysis? I am analyzing the VDD pin of an IC and t...
    xenxo
    last modified by xenxo
  • Missing Reference Layer

    Good morning,   I am trying to carry out a distributed decoupling analysis. The "Decoupling Wizard" warns me that there is no reference layer on that particular power pin. However, I can clearly see the referenc...
    xenxo
    last modified by xenxo
  • plane noise analysis principles

    Hello,   I would greatly appreciate for a a more detailed explanation on how to interpret the plane noise analysis in hyperlynx. In my opinion it would be great if information provided in the product help and t...
    rasputin83
    last modified by rasputin83
  • How does Hyperlynx define "Rise Rail Overshoot"?

    In a simulation, the rise rail overshoot is nearly -2V for some signals. I am trying to understand the exact meaning of this parameter and how it correlates to the actual overshoot of this signal.   Thanks
    kyleremich
    last modified by kyleremich
  • ODT model selection????

    I am new to hyperlynx!! What is the significance of ODT model selection during DDRx batch simulation? And also ODT behavior? It will be a great help if you explain in detail.
  • LPDDR3 EBD Model Assignment Issue

    I am first time user of EBD files in Hyperlynx. The LPDDR3 model I'm using was provided from a supplier in a zip. I have imported layout (.brd file) into hyperlynx. LPDDR3 and processor are on same board. I have ...
    n_jadhav_jhnn7
    last modified by n_jadhav_jhnn7
  • BCI Test Analysis

    Hi everyone, We need to check the layout for BCI test. I have a board that can't pass this test all the time, I've tried many ways to pass it using CMC, LC, FB filters. Finally, the other day, I measured between the ...
    gokhannsahin
    last modified by gokhannsahin
  • Decoupling Capacitor Model Type

    Hello, I have recently started to use HyperLynx so I apologize in advance if the following questions are basic. There are 3 types of Models for the capacitors: 1) Simple C-LR    The capacitance value, is...
    xenxo
    last modified by xenxo
  • If IBIS model is not available?

    I have to do SI Analysis for communication Signals, but i have n't found Ibis model for that IC. Can any one pls tell me is there any method in hyperlynx to do the analysis without IBIS model. Actually iam using cmos ...
    ecs
    last modified by ecs
  • Termination

    hi, i have small doubt regarding termination, for bi-directional signals whether we can use series termination at both driver & receiver IC or not ? is there any other termination we can use?     than...
    ecs
    last modified by ecs
  • If IBIS Model is not avaliable?

    Hi, I am doing the SI analysis for communication Signals, but i have not found the ibis model for required IC, is there any possible method in hyperlynx to do the analysis without IBIS model. Actually i doing the ana...
    ecs
    last modified by ecs