• How to deal with the AC capacitor in a serial link?

    Hi Guys,     I'm really confused by the AC capacitor in a serial link, who can detail its function?  In our simulation,how to deal with it?     I want to use the S parameter model,...
    last modified by bruce_qin
  • DDRx batch sim producing erroneous delay values.

    I have been scratching my head for a couple days now... I set up the DDRx simulation based on my design (included IBIS models, created controller timing model, etc.) and most of the results from simulation make sense ...
    last modified by nadroj5
  • Field Solver Issue

    I'm trying to select a net and run Field Solver to get the trace capacitance and delay values from each net. But I can only do that for each small segment of the entire net. Is there a way I can select the entire net ...
    last modified by victorho55
  • DDR3 Timing Models

    I am simulating a DDR3L interface between a Xilinx XCKU085 and a Micron MT41K512M8DA. I do not have the timing model for the FPGA controller so I am using the generic ones that came with Hyperlynx. The design pas...
    last modified by igby
  • DDRx Batch simulation results

    Hello all, I am using DDRx Batch simulations to simulate Alliance memory's AS4C512M16D3L-12BIN DDR3L with NXP's processor T1042.  I am applying some sweaps to check which terminations resistors should I use and w...
    last modified by m.ather
  • How to mark the series inductance to recognize its another net as VRM ?

    Hello, After simulating signal-via bypassing (Simulate PI > Analyze Signal-Via Bypassing), I see the following lines in the resulting report (BW.log): ... Processing VRMs for transmission plane with layers "SIGNA...
    last modified by olsmir
  • Opening a Database in Waveform Analyzer using script

    How to open a text or *.csv file in Waveform Analyzer using a script. manually we can use open and select that file to open as database. it would be really great if you help me to do the same using a script
    last modified by rithesh
  • Missing driver model in Generic Batch Simulation

    Dear the experts,   I use the Generic Batch simulation to run the crosstalk quick analysis for DDR4 in the board sim. I have met the issue below: I have implemented all workaround base on below link but this...
    last modified by hungreohd
  • AC analysis

    Hi All,   When to use Gaussian pulse ? Is there any specific situation to use it. I am bit confused to selecting between pulse shapes.. I have a IBIS model for FPGA i can attach it in board sim and  can...
    last modified by shravan.sk
  • VRM Assignment in DC Drop

    Hello,   I am working with DC Drop simulation, I have queries regarding VRM assignment.   In Simple Model how can i get resistance and inductance value?can we get it from datasheet?   In Advanced Mod...
    created by shravan.sk
  • DDRx Batch Mode Diff pair error

    Hello I'm trying to run the DDRx Batch Mode Wizard but the Diff pairs aren't detected as is shown on the images This happens for the clk signals too. Is there a configuration that I need to do in order to get the di...
    last modified by eduardo_teo
  • Plane noise analysis

    Hi expert,   Recently, I have been studying plan noise simulation in Hyperlynx but I don't know how to specify an AC model for power pins. I have searched some materials but all of them don't mention about that...
    last modified by tyle
  • Specifying value for power supplies

    In the Edit Power-Supply Nets dialog (Setup > Power Supplies), my net +0.85VD has been successfully recognized as power supply, and in the Voltage column I see <0.85>. Should I delete <...
    last modified by olsmir
  • How is "Multi Cross Threshold" PASS/FAIL connected to driver strength?

    Hi, With HyperLynx vers. 2.5, I have run "General Batch Simulation" between processor and LPDDR4. One specific result came up which I could not understand nor explain. The simulation-result showed our design ha...
    last modified by puiyee
  • BoardSim VX2.3: How do I remove a model assigned by net?

    I accidentally assigned a model "by net" for my component. I intended to (and eventually did) assign the component by reference designator, and then I changed the model under the ref des. Now I'm using the DDRx Batch ...
    last modified by t_blikstad
  • error while simulating PCIe signals

    Hi,      I am trying to simulate eye diagram for  PCIe(gen2), between 2 FPGA's(XC7K410T-2FBG900C) on separate boards. There is a driver(DS80PCI402SQ/NOPB) on one board for the PCIe signals. O...
    last modified by judson_antu
  • Meshing error in Full Wave Solver

    Hi,   I am facing this issue while meshing Error: Invalid mesh.  : Connection with empty termination All the ports have 50 ohm termination assigned by the tool itself Mesh Validity check had passed. Ca...
    last modified by ashish_02007
  • LPDDR4 Monotonic Failure

    Hello, I'm running LPDDR4 DDRx batch simulation and seeing a monotonic failure for the Differential pair in slow corner  .The waveform looks good to me, please see the attached .     Thanks
    last modified by yerkares
  • Intel CPUs DDR Simulation

    Hello,   We want to make DDR simulation using Intel CPUs however Intel does not provide full IBIS models for CPUs. It provides DDR package model with .sp and .inc files. Are there any available document / guide...
  • Adding Parasitic Resistances

    Hi,   I have been using the PI tool for a little while, and it would be very helpful if there were an easy way to assign parasitic resistances to the inductors on my board.  Is there anyway to do this in Hy...
    last modified by matthewd49