• HyperLynx Thermal

    Why does HyperLynx Thermal does not take negative Temperatures? When I try to enter a negative number (-40 for example), the GUI records 0 instead. If this is a bug on the GUI, please address it because the automoti...
    c_nzeyimana
    last modified by c_nzeyimana
  • Sense Connection

    Hello Experts,   Can we simulate DC drop considering effect of voltage sense connection in hyperlynx?   Regards, SK .
    shravan.sk
    last modified by shravan.sk
  • IBIS-AMI MODEL ASSIGNMENT

    DURING IBIS-AMI CHANNEL ANALYSIS  .ami AND .dll ASSIGNMENTS I AM RECEIVING AN ERROR THAT "YOUR DLL REQUIRES AN ANOTHER .DLL THAT IS NOT PRESENT " KINDLY GUIDE REGARDS#
    engr.adam76@gmail.com
    last modified by engr.adam76@gmail.com
  • With respect to HyperLynx SI/PI, what is the difference between .hyp and .cce files? Is one better than the other?

    hyperlynxsignalintegrity For Signal Integrity simulations which one is better *.cce or *.hyp? Which file is better for sharing information?
    narasimhamurthy
    last modified by narasimhamurthy
  • EMI/EMC/Antenna Simulation

    Hello Team,   Can we perform EMI/EMC and Antenna Simulation in Hyperlynx advanced solver?   If yes,Please guide me to simulate.   Regards, SK
    shravan.sk
    last modified by shravan.sk
  • Hyperlynx : DRR3 Batch Simulation Data Read Problem

    We are simulation DDR3L in our design and we are trying to simulate our chips through Hyperlynx DDR3 batch simulation. We have used one slot dual ranked settings. After setting the parameters required for DDR3 batch s...
    m.ather
    last modified by m.ather
  • Digital Oscilloscope maximum oscillator frequency

    HI, I have a SDI 12 GHZ to simulate, can i setup the Oscillator frequency at 12000 Mhz ? Thanks
    stephane
    last modified by stephane
  • Does HyperLynx take via stubs into account? If so, how?

    I'm running an HL simulation (HyperLynx SI/PI/Thermal VX.2.4_Update 1) of a PCIe Gen 2 link running across a VPX backplane. It does not seem to take the via stubs into account, and I want to know if I'm doing somethin...
    daleb777
    last modified by daleb777
  • Ground Vs. Power Planes & Impedance

    I note that Hyperlynx LineSim does  not differentiate between power and ground planes in a layer stackup.   Does this mean there is no difference between power and ground planes  when defining a co...
    dupre
    last modified by dupre
  • Via Modeling

    Hi,  I want to do via modeling in Hyperlynx Full Wave Solver VX2.3 for 20 layer board.  Here we have 2 kind of Layer transition on via as L1 to L16 and L1 to L18 for same via structure.  Should I do ...
    sivasankars
    last modified by sivasankars
  • Board level thermal

    we wan to add polymide laminate that has low CTE.How to embed low CTE value and perform board level thermal analysis.
    rj&j
    created by rj&j
  • Quarter wavelength rule?

          I know something about the mysterious quarter wavelength rule, it is usually to be said as: when routing high speed signal trace, the trace length must be avoided to become integral mult...
    bruce_qin
    last modified by bruce_qin
  • How to deal with the AC capacitor in a serial link?

    Hi Guys,     I'm really confused by the AC capacitor in a serial link, who can detail its function?  In our simulation,how to deal with it?     I want to use the S parameter model,...
    bruce_qin
    last modified by bruce_qin
  • DDRx batch sim producing erroneous delay values.

    I have been scratching my head for a couple days now... I set up the DDRx simulation based on my design (included IBIS models, created controller timing model, etc.) and most of the results from simulation make sense ...
    nadroj5
    last modified by nadroj5
  • Field Solver Issue

    I'm trying to select a net and run Field Solver to get the trace capacitance and delay values from each net. But I can only do that for each small segment of the entire net. Is there a way I can select the entire net ...
    victorho55
    last modified by victorho55
  • DDR3 Timing Models

    I am simulating a DDR3L interface between a Xilinx XCKU085 and a Micron MT41K512M8DA. I do not have the timing model for the FPGA controller so I am using the generic ones that came with Hyperlynx. The design pas...
    igby
    last modified by igby
  • DDRx Batch simulation results

    Hello all, I am using DDRx Batch simulations to simulate Alliance memory's AS4C512M16D3L-12BIN DDR3L with NXP's processor T1042.  I am applying some sweaps to check which terminations resistors should I use and w...
    m.ather
    last modified by m.ather
  • How to mark the series inductance to recognize its another net as VRM ?

    Hello, After simulating signal-via bypassing (Simulate PI > Analyze Signal-Via Bypassing), I see the following lines in the resulting report (BW.log): ... Processing VRMs for transmission plane with layers "SIGNA...
    olsmir
    last modified by olsmir
  • Opening a Database in Waveform Analyzer using script

    How to open a text or *.csv file in Waveform Analyzer using a script. manually we can use open and select that file to open as database. it would be really great if you help me to do the same using a script
    rithesh
    last modified by rithesh
  • Missing driver model in Generic Batch Simulation

    Dear the experts,   I use the Generic Batch simulation to run the crosstalk quick analysis for DDR4 in the board sim. I have met the issue below: I have implemented all workaround base on below link but this...
    hungreohd
    last modified by hungreohd