Log in to follow, share, and participate in this community. Hello, I'm running LPDDR4 DDRx batch simulation and seeing a monotonic failure for the Differential pair in slow corner .The waveform looks good to me, please see the attached . Thanks Hello, We want to make DDR simulation using Intel CPUs however Intel does not provide full IBIS models for CPUs. It provides DDR package model with .sp and .inc files. Are there any available document / guide... Hi, I have been using the PI tool for a little while, and it would be very helpful if there were an easy way to assign parasitic resistances to the inductors on my board. Is there anyway to do this in Hy... When I run Simulate PI->DC Drop for Multiple Nets with Combined Ground Currents with a ground net and all of its associated power nets selected, the pins on some of the power nets appear as DISCONNECTED on the resu... We have a schematic, with 3 s-parameter models in it. Its a differential Channel and the s-parameter models are 3x 3D differential Via models interconnected by diff pair traces. an IBIS driver and an IBIS... Hi, I have a query regarding addition of flight time compensation while doing timing analysis using batch mode simulation. I can find the option to add the flight time compensation in the batch mode wizard of... Dear Experts, I try to simulate PDN by lumped and distributed analysis with simple RLC and S-parameter model for the capacitor. Please see the result in the picture below: my Ztarget = 0.93 * 0.05 / (0.5 *... I am currently using Hyperlynx Boardsim X.2.4 to simulate a DDR3 design with an iMX6 processor connected to two DDR3 ICs. The routing topology is with a single T branch for address control and clock. The differential ... According to https://support.mentor.com/en/knowledge-base/mg564105 there are times that you might need to change the layer setting based on your simulation scenario and how the reference planes should be recognized.... I'm using HyperLynx vx2.3. I would like to be able to mark a component as depopulated, or delete it entirely, on a board I imported from CR-5000 board files. I successfully imported the board and can r... I am trying to understand what "bad signal " means and how to fix this error? Thank you. As for bsw.ini, its local copy can be perfectly specified through HYPERLYNX_INI for each user. But what about other ini files? For example, when invoking Touchstone Viewer (File > Edit Touchstone Models), the Touch... We have HyperLynx VX.2.3_Update2 installed in a centralized location (/opt/...) with multiple users to be able to run from there. I have a couple of set up questions for each new user (all of these defaults each time... I have a IBIS model in .dll format. And not be able to assign that as a ibis model in Hyperlynx. Any idea how to do that ? I need it for SI simulation. Vendor provided me .dll file instead of .ibs file Dear Team, I am doing PCB Level thermal simulation. I am keeping initial temperature as 35 deg C and Casing wall Temperature (Ambient Temperature) as 70 deg C. The system is a closed system with single board wi... Hello, I'm a newbie with HyperLynx and am trying to run a simulation on an LVDS clock. Can anyone suggest what model from the libraries should I select? Thanks, Joe Hello all, I am using DDRx Batch simulations to simulate Alliance memory's AS4C512M16D3L-12BIN DDR3L with NXP's processor T1042. I am applying some sweaps to check which terminations resistors should I use and w... Dear Mentor Support Team, I am very interested to know and find a solution to simulate the effect split plans and gaps in Signal Integrity, Power integrity and EMI. I would like also to know if there is a sol... Hi All, So recently I raised a mentor support ticket how can I quantify the effect of a high-speed signal crossing a split plane on a PCB with a star ground. I got a reply from Mentor that you can not do it in Hyper... Also check the probe location, DDRx batch simulation probably uses the die as probe location while the default setting in the scope is 'always at pin'