• DDRx Batch Mode Diff pair error

    Hello I'm trying to run the DDRx Batch Mode Wizard but the Diff pairs aren't detected as is shown on the images This happens for the clk signals too. Is there a configuration that I need to do in order to get the di...
    eduardo_teo
    last modified by eduardo_teo
  • Plane noise analysis

    Hi expert,   Recently, I have been studying plan noise simulation in Hyperlynx but I don't know how to specify an AC model for power pins. I have searched some materials but all of them don't mention about that...
    tyle
    last modified by tyle
  • AC analysis

    Hi All,   When to use Gaussian pulse ? Is there any specific situation to use it. I am bit confused to selecting between pulse shapes.. I have a IBIS model for FPGA i can attach it in board sim and  can...
    shravan.sk
    last modified by shravan.sk
  • Specifying value for power supplies

    In the Edit Power-Supply Nets dialog (Setup > Power Supplies), my net +0.85VD has been successfully recognized as power supply, and in the Voltage column I see <0.85>. Should I delete <...
    olsmir
    last modified by olsmir
  • How is "Multi Cross Threshold" PASS/FAIL connected to driver strength?

    Hi, With HyperLynx vers. 2.5, I have run "General Batch Simulation" between processor and LPDDR4. One specific result came up which I could not understand nor explain. The simulation-result showed our design ha...
    puiyee
    last modified by puiyee
  • BoardSim VX2.3: How do I remove a model assigned by net?

    I accidentally assigned a model "by net" for my component. I intended to (and eventually did) assign the component by reference designator, and then I changed the model under the ref des. Now I'm using the DDRx Batch ...
    t_blikstad
    last modified by t_blikstad
  • error while simulating PCIe signals

    Hi,      I am trying to simulate eye diagram for  PCIe(gen2), between 2 FPGA's(XC7K410T-2FBG900C) on separate boards. There is a driver(DS80PCI402SQ/NOPB) on one board for the PCIe signals. O...
    judson_antu
    last modified by judson_antu
  • Meshing error in Full Wave Solver

    Hi,   I am facing this issue while meshing Error: Invalid mesh.  : Connection with empty termination All the ports have 50 ohm termination assigned by the tool itself Mesh Validity check had passed. Ca...
    ashish_02007
    last modified by ashish_02007
  • LPDDR4 Monotonic Failure

    Hello, I'm running LPDDR4 DDRx batch simulation and seeing a monotonic failure for the Differential pair in slow corner  .The waveform looks good to me, please see the attached .     Thanks
    yerkares
    last modified by yerkares
  • Intel CPUs DDR Simulation

    Hello,   We want to make DDR simulation using Intel CPUs however Intel does not provide full IBIS models for CPUs. It provides DDR package model with .sp and .inc files. Are there any available document / guide...
  • Adding Parasitic Resistances

    Hi,   I have been using the PI tool for a little while, and it would be very helpful if there were an easy way to assign parasitic resistances to the inductors on my board.  Is there anyway to do this in Hy...
    matthewd49
    last modified by matthewd49
  • Some power nets getting disconnected when running DC Drop Simulation for Multiple Nets

    When I run Simulate PI->DC Drop for Multiple Nets with Combined Ground Currents with a ground net and all of its associated power nets selected, the pins on some of the power nets appear as DISCONNECTED on the resu...
    willdecook
    last modified by willdecook
  • Export S- parameter

    We have a schematic, with 3 s-parameter models in it.  Its a differential Channel and the s-parameter models are 3x 3D differential Via models interconnected by diff pair traces.  an IBIS driver and an IBIS...
    crouchingtiger
    last modified by crouchingtiger
  • Flight time compensation in hyperlynx VX_2.3

    Hi,   I have a query regarding addition of flight time compensation while doing timing analysis using batch mode simulation. I can find the option to add the flight time compensation in the batch mode wizard of...
    shanmugapriyaaa
    last modified by shanmugapriyaaa
  • Understanding difference between lumped and distributed decoupling analysis with simple R-L-C or S-parameter model

    Dear Experts, I try to simulate PDN by lumped and distributed analysis with simple RLC and S-parameter model for the capacitor. Please see the result in the picture below:   my Ztarget = 0.93 * 0.05 / (0.5 *...
    hungdang1506
    last modified by hungdang1506
  • Issue with Clock / Address / Command Group in DDR3 Simulation

    I am currently using Hyperlynx Boardsim X.2.4 to simulate a DDR3 design with an iMX6 processor connected to two DDR3 ICs. The routing topology is with a single T branch for address control and clock. The differential ...
    mwill195
    last modified by mwill195
  • Mixed signal/plane layer setting

    According to https://support.mentor.com/en/knowledge-base/mg564105 there are times that you might need to change the layer setting based on your simulation scenario and how the reference planes should be recognized.&#...
    jg_eng
    last modified by jg_eng
  • HyperLynx Vx.2.3: How do I delete a component (or mark unpopulated) on an imported board?

    I'm using HyperLynx vx2.3.   I would like to be able to mark a component as depopulated, or delete it entirely, on a board I imported from CR-5000 board files.   I successfully imported the board and can r...
    t_blikstad
    last modified by t_blikstad
  • DDRx Wizard analysis: Bad signal?

    I am trying to understand what "bad signal " means and how to fix this error?   Thank you.
    gurushankar
    last modified by gurushankar
  • Important note: Multi-user environment and localized settings with centralized installation.

    As for bsw.ini, its local copy can be perfectly specified through HYPERLYNX_INI for each user. But what about other ini files? For example, when invoking Touchstone Viewer (File > Edit Touchstone Models), the Touch...
    olsmir
    last modified by olsmir