• XPEDITION VX 2.6

    How to archive DxDesigner project file with you and PCB template. Every time EE sends updated file, it comes with 8 layer PCB template. Were actual PCB is 16 layer. once new schematic file comes from EE again, layer s...
    pgovani007
    last modified by pgovani007
  • Bank Painter for Xpedition/PADS Professional

    Hello again, As I stated while sharing Outline Assigner for Xpedition/PADS Professional, we have decided to open source some components of our PCB Automation stack. In this post, I'm sharing Bank Paint...
    FUAT SENGUL
    last modified by FUAT SENGUL
  • Outline Assigner for Xpedition/PADS Professional

    Hello, we decided to open source some components of our automation stack with believe to help others. This software helps Xpedition/PADS Pro users to make their life easy and happy when it comes to small but impo...
    FUAT SENGUL
    last modified by FUAT SENGUL
  • In Xpedition layout, when does a plane island DRC error (In Batch DRC) happen?

    In Xpedition layout, when does a plane island DRC error (In Batch DRC) happen? Please see attached screen dump for more info.
    kartik_
    last modified by kartik_
  • Updating Border Symbols for Managed Blocks in xDX Designer V2.6

    Hi,   I'm using Managed Blocks to create an overall Top Level Schematic in xDX Designer V2.6. The Managed Blocks themselves don't have any fixed border and the border setting is done for the host schematic ...
    t_ghose_duf7c
    last modified by t_ghose_duf7c
  • Convert 2005.3 to VX2.4

    Can Mentor databases done in 2005.3 be converted into VX2.4 ?   Or must it be a stepped approach from 2005.3 to EE7.9 to VX2.4 ?
    kman
    last modified by kman
  • Application disconnected detected - sch2pdf.exe

    Hey   i execute the sch2pdf.exe by the mgcscript.exe on a prj (VX2.4) on each variant in the design. the pdf files are exported successfully, but the Mentor Graphics iCDB Server Monitor raise error message. "A...
    longjohn
    last modified by longjohn
  • How to control fanout via span?

    Hello, anybody know how i can automatically do fanout with stacked vias?
    pbo
    last modified by pbo
  • Script.ini file subleties

    HI,   I'm building custom toolbars for both Xpedition Layout and Designer. I've found that I can simply add my script paths into the script.ini file, so they are run on program launch.   I've noticed that ...
    nhirsch
    last modified by nhirsch
  • Differential pairs not recognized in Constraint Manager

    Hello!   I have a board with several differential signals. When I opened the Xpedition Constraint manager I noticed that Xpedition does not recognize some of the differential signals. See below. You can see the ...
    kyndal6
    last modified by kyndal6
  • Databook Search for keywords

    I remember something in the trainings, but I cant seem to find it. My company uses Xpedition with a databook containing all approved parts. I need to find a barrel connector, but no combination of >=, =, <=, !=,...
    latter_version
    last modified by latter_version
  • Looking for research study participants

    Siemens Digital Industries Software would like to hear from you!   Thank you for being a valued member of our community. We’re inviting 10 Mentor Graphics and Siemens Digital Industries Software customers ...
    Community_Admin
    created by Community_Admin
  • How to add User defined Layer in Script file to generate Gerber

    Hello All, Iam creating Script file which will generate Gerber Files. But i want to add some User Layer in Gerber files but iam not able to do this. Can you please let me know how to add user-layer into Gerber scri...
  • Netlist Comparison

    Hello All, Is there anyone have script or any other thing  for Netlist comparison.
  • How to Convert from Pads 9.5 to Xpeditionn Vx2.4

    Please share the document to convert from PADs 9.5 to Xpedition Vx2.4
    y_balasubramaniam_qbllk
    last modified by y_balasubramaniam_qbllk
  • Chip Embedding support and copper inlay

    Hi there, is any possiblity in Xpedition to route board with embedded chips? I just cant find way around this. Ive managed to just draw area where chip should be and made some vias to "noting" DRC is not happy at all...
    m_kovarik_mjnvl
    last modified by m_kovarik_mjnvl
  • Migration from Cadense Allegro 17.2 to X-ENTP VX.2.7

    Hi, I am very new to Xpedition platform and installed X-ENTP VX.2.7 (64-bit) in my windows 10 PC. I have an old design in Cadence Allegro capture 17.2 and now I have to migrate to Xpedition and modify the design. Plea...
    shyjukm
    last modified by shyjukm
  • Complex via - Net name assignment for shielding

    How to assign net name for vias defined in shielding of complex via (In single shot)?
    pravm
    last modified by pravm
  • GitHub Version Control

    Has anyone ever tried to set up version control for Xpedition/PADS Professional projects via Github? How do I make this setting right?
    pbo
    last modified by pbo
  • Exclude a specific string by regular expression

    Hello, I'm trying to get familiar with the Regular Expression on Property Definition Editor. I saw that it is possible to exclude a list of characters through the syntax [^abcd]* This way if I write any string that c...
    piffi
    last modified by piffi