• VX2.3: gray FPGA-box prevents connections after moving FPGA-symbol

    Hello,   since upgrade from VX2.2 to VX2.3 our FPGA-symbols have got a gray box (1). What is this for? That gray box prevents automatically connecting (3) of a disconnected FPGA-symbol (2). How can i remove th...
    last modified by heer
  • How to DNI all parts at once using part exclude property

    Hi How to DNI the parts using part exlude property not using variants. Manually adding part exclude to so many components takes lot of time. Is there any way to add part exclude to all the components at once to DNI...
  • xDX FPGA IOPT workflow in VX.2

    There are two ways how to use the IOPT for FPGAs.  Either generate all symbols in the IOPT tool and add it to schematic or use symbols created in Library Tools (Symbol Editor or FPGA part wizard) and import it to...
    last modified by lanelone
  • BOM with cell name property

    hi all,   anyone can help to solve the issue to have cell name in the bom (generated by part lister) when the symbol does not have the cell name attached to it. Thanks in advance.
    last modified by vivian
  • How to create symbols for semi configurable IC's, like i.MX6?

    Today's ASIC controllers are highly configurable and are more a mixture between FPGA and standard IC microcontroller. An example of that new devices is the i.MX6 from Freescale. This chip has got about 625 pins. 32 of...
    last modified by thomas.te.ebert
  • How to assign all unassigned pins to signals in IO Designer?

    Hi all,   In IO Designer after importing the UCF file, only one pin is assigned to signal from power and ground group. Remaining pins are in unassigned pins list.   What is the easy method  to assign...
    last modified by bmurali1011
  • Replacing bank of symbols

    Hai how can i replace a bank of symbols by using replace command. regards Sajiv
    last modified by sajivnglnice
  • How to make special assignments (unused pins to GND or NC)?

    Hello,   We would like to connect some of the unused or special pins to GND. Some other unused pins we want to keep them NC. How should we do that in IOD/DxDesigner for Expedition flow? For example we would like ...
    last modified by cristian.filip
  • Pin Assignments

    Hai,   While importing ucf file in IO designer, it assign a single pin for GND net. That is the GND net having only one pin only. So i manually assigns each pins to GND. It takes more time for me, because more t...
    last modified by bmurali1011
  • Assigning bank supply voltages

    Hai,   I use artix7 fpga for my project. While swapping nets by means of IO Designer i need to assign supply voltages for the banks. I planned to use VCCINT and VCCBRAM for same supply voltage. I  assigned ...
    last modified by sajivnglnice
  • Power and Ground nets disconnected in schematic while Exporting scematic update

    Hai,   While  exporting schematic update(after unravel)  all the supply and gnd nets gets disconnected in schematic(Dxdesigner). Will be there any method to avoid this. Please help me.   Regards...
    last modified by sajivnglnice
  • io designer

    Hi            I Have an option called io designer how to use this for FPGA Pin swapping Can I use it for connector pin swapping thanks and regards agxin j
    last modified by agxinmj
  • transfering direction (pin type) to DxDesigner Symbols

    I would like to know if it's possible to get the value of the DIR attribute to the generated DxDesigner symbols?   It would be extremly useful for board designers to get the values (IN,OUT, BI) for the signals v...
    last modified by thomas.te.ebert
  • the need to rename pcb symbols

    Is there any plan to change I/OD so pcb symbols do not have to be renamed when pins are added or removed after initial exportation?
    last modified by john.kool
  • How can I use IOD to optimize connectivity between two connectors (without any FPGA) ?

    Hello, How can I use IOD to optimize connectivity between two connectors (without any FPGA) ?   Best regards, mwalczak
    last modified by mwalczak

    Trying to get a Xilinx Kintex part set up in a Schematic Upate process. I have things functioning for the most part- signal updates do their thing- but IOD seems to have no idea what to do with the VCCBRAM power pins,...
    last modified by michael.j.holmes
  • problem with the build in Altera Pinning Rules and DDR-II Interface

    Hello,   I have a problem with the IO-Mapping of a existing FPGA Design (Altera / Cycole IV E 40K). The IO-Designer don't Map some Pins because he mean that this Pin mapping is against some Altera Mapping Rule ...
    last modified by o.mahren
  • I/O Designer in a PADS Flow - opening questions

    Dave & Frank,   Thanks for taking the time & effort to set this discussion thread up.  In the many customer interactions I have encountered, high pin count FPGAs devices are definitely a challenge ...
    last modified by John_Peloso
  • How to build a filter based on negation

    I have opened the Virtex-6 database in IODesigner. I need to build a filter that would list all unused user pins in the Pins window. For this, I have written the following filter in Setup > Settings > Filters &g...
    last modified by olsmir
  • Unravel based on partial routing

    In I/O Designer is it possible to unravel nets based on partial routing? For example, if netlines are connected to the top left of a device but the partial routing is directed towards the bottom right, will unravellin...
    last modified by simon.hawkes1