• Managed blocks: Error 12002: Ripper has an invalid bus reference

    Hello everyone,   I'm working with two of my colleagues on one PCB. Each one of us works on a different part of the design and we're trying to use managed blocks to bring everything together.   One thing I...
    fgrossmann@men.de
    last modified by fgrossmann@men.de
  • Unable to hide "Name" on Nets since VX.2.4

    Before I create a SR with that Bug, I ask if it's a feature, which I can anywhere deactivate!? ... And after the re-select in Schematic, the checkbox is still checked!!!      We think it's ...
    juergen.hinterleitner
    last modified by juergen.hinterleitner
  • Move Net names Xpedition Designer VX.2.3

    I am unable to move my net names on each of my nets without dragging my net with it. Its like the net name is anchored to the net its self. Is there a setting where I can move the net name anywhere I like without ...
    jcbell
    last modified by jcbell
  • How to define "Not Place" or "not load" to parts on Schematics Dx Designer VX2.1?

    I'm new to DxDesigner. I want to show on schematics that the part shall not be placed, although the pads remain (with a X over the part or text saying "no load"). Also, I want this to be linked to that single part, so...
    jhonathan
    last modified by jhonathan
  • Variant Manager substitution question.

    Can Variant Manager be used to substitute parts that have pins swapped?   I've never used VM for this but I'm working on a design where a previous designer had a local reuse block (four instances) that...
    steve_bonacci
    created by steve_bonacci
  • xDx Designer - hierarchical design - Packager issue ?

    Hello Community,   I have some trouble in my current schematic under VX.2.1. This time I need a hierarchical design approach. My problem is illustrated below with one connector, which consits of two symbol...
    fuba
    last modified by fuba
  • Schematic Nets - go to which sheets?

    I'm a newbie to Mentor Xpedition Designer.   I'm starting a new schematic. Its not too big so I don't need hierarchy, just a flat design over several sheets.   I want to ensure that nets from one sheet con...
    d.cooke
    last modified by d.cooke
  • How to make multiple schematics in a single board in dxdesigner

    My question is how to make multiple schematics in a single board in dxdesigner.   I'd like to make hierachical design below.....     DxDesigner's Navigator       Project Name...
    marx
    last modified by marx
  • ERROR: Unable to locate CES pin

    Hi,   I'm getting a strange error when packaging for which I can't find any information. I'm getting a bunch of:   ERROR: Unable to locate CES pin "R???-?" while  attempting to connect pin to net "???...
    mathieu.lafrance
    last modified by mathieu.lafrance
  • System Added Net Names Caused a Short

    Hi,  I have a schematic that has one particularly large circuit that was copied four times. The circuit was laid out and net names were added to certain nets. Off sheet connectors were added to nets that should c...
    wayne_5757
    last modified by wayne_5757
  • Facing difficulties in schematic pdf creation

    I am using Xepedition ,but I am facing difficulties in schematic pdf creation. If font style kept on "System " then all font sizes increased in pdf as shown in figure.   So please suggest, If is there any ste...
  • The end of life for Design Capture?

    Can someone confirm the mentor decision to decommission design capture and the end of support? I will assume at this point customers will have access to keys to view sustaining projects or supplement for translatio...
    chris.smith
    created by chris.smith
  • how to export local symbol into central library

    Hi there, I am using VX2.4 , update 2.   Somehow my border symbol got corrupted in the central library (the symbol is still there in the library tree but it appears as blank). Luckily I have a Designer project...
    stempialdo
    last modified by stempialdo
  • schematic verification

    Good afternoon everyone. I have a question on schematic verification and setting up the rules properly using the verifydefaults.ini We've been rebuilding our library from scratch and trying to incorporate the correc...
    cgoldenbus
    created by cgoldenbus
  • component highlight in designer

    When you select a component in designer it "highlight's" the part I guess by bringing it to the front so everything else around it is now darker. Our engineering staff really dislikes this "feature" I know of no way t...
    cgoldenbus
    last modified by cgoldenbus
  • Control of Text Visibility in DxDesigner

    Does anyone have a way to control Text (annotation) Visibility during PDF creation or while using DxDesigner?  What I am looking for is a way to add text notes for certain customers of the schematic such as Test,...
    ted_casper
    last modified by ted_casper
  • Variant Manager - option 'Auto_Unplace' will always be activated! (uncontrollable)

    Again and again on different designs, when we open the VariantManager, the option is set to "<Auto_Unplace>". But when we set it to "<Select>", after re-opening the VariantManager, it will be automatically...
    juergen.hinterleitner
    last modified by juergen.hinterleitner
  • Setting pin direction on connectors & FPGAs overriding bidi defaults for DRC checks

    How can I set pin directions in a DxDesigner schematic to get DRCs working on pins that are set to bidi in the part library? Connectors and FPGAs typically have IOs set to bidi in the part library. However, for a par...
    mives
    last modified by mives
  • Odd number of brackets in bus name , but there is no bracket in bus name

    Though bus name doesn't have the brackets ,DRC output shows    Odd number of brackets in bus name: BUS_GPIO_EXPANDER_I2C   But,It is connected properly between two blocks.  
    ramachandran
    last modified by ramachandran
  • Variant Manager Bom Report

    Hi all,   We generate a BOM Report from the Variant Manager Grid. And no we experience a very irritating phenomena. Look at this snippet of the BOM reports.     it apppears that it cannot handle pf ...