• The end of life for Design Capture?

    Can someone confirm the mentor decision to decommission design capture and the end of support? I will assume at this point customers will have access to keys to view sustaining projects or supplement for translatio...
    chris.smith
    created by chris.smith
  • schematic verification

    Good afternoon everyone. I have a question on schematic verification and setting up the rules properly using the verifydefaults.ini We've been rebuilding our library from scratch and trying to incorporate the correc...
    cgoldenbus
    created by cgoldenbus
  • component highlight in designer

    When you select a component in designer it "highlight's" the part I guess by bringing it to the front so everything else around it is now darker. Our engineering staff really dislikes this "feature" I know of no way t...
    cgoldenbus
    last modified by cgoldenbus
  • Control of Text Visibility in DxDesigner

    Does anyone have a way to control Text (annotation) Visibility during PDF creation or while using DxDesigner?  What I am looking for is a way to add text notes for certain customers of the schematic such as Test,...
    ted_casper
    last modified by ted_casper
  • Variant Manager - option 'Auto_Unplace' will always be activated! (uncontrollable)

    Again and again on different designs, when we open the VariantManager, the option is set to "<Auto_Unplace>". But when we set it to "<Select>", after re-opening the VariantManager, it will be automatically...
    juergen.hinterleitner
    last modified by juergen.hinterleitner
  • Setting pin direction on connectors & FPGAs overriding bidi defaults for DRC checks

    How can I set pin directions in a DxDesigner schematic to get DRCs working on pins that are set to bidi in the part library? Connectors and FPGAs typically have IOs set to bidi in the part library. However, for a par...
    mives
    last modified by mives
  • Variant Manager Bom Report

    Hi all,   We generate a BOM Report from the Variant Manager Grid. And no we experience a very irritating phenomena. Look at this snippet of the BOM reports.     it apppears that it cannot handle pf ...
  • Xpedition Partlister problems with instance values

    I am trying to create a BOM with Partslister in Xpedition Designer VX2.2. To create different variants, I am using the variant manager in "Create Varaint/Function Schematics"-mode and start then the Partlister. My...
    eaton_mentor
    last modified by eaton_mentor
  • Package error

    ERROR: There is no Part Number: 1006962 in the Parts DataBase for symbols with Part Name: xc7z030-1ffg676c and Part Label: FPGA. [Please add the Part Number to the PDB either directly or by having the project file poi...
    charles.ietswaard1
    last modified by charles.ietswaard1
  • Missing DA2DX Converter in VX.2.5 =:-o

    Since 2.5 I don't find the "da2dx.exe" anymore. So I checked, if I'd forgotten to install the translator - but then I realized, that Mentor has removed the Install-group "Translators" (in the Setup where you choose th...
    juergen.hinterleitner
    last modified by juergen.hinterleitner
  • add "cell overhang" for existing cell

    Hi there,   does anybody know how to add the "cell overhang" property to a cell that already exists in the library? I can only find that option when creating a new cell.   The cell editor manual it says "...
    stempialdo
    last modified by stempialdo
  • Proper offsheet or onsheet symbol usage?

    What is the proper way to use offsheet and onsheet symbols (in the common library)?  I.e., how do I get them to link nets across pages? I keep getting a warning that "NETNAME on annotate component will not label...
    mchambers
    last modified by mchambers
  • xDX designer is in readonly mode

    Hi,   I run into this problem today when re-opening my design. it suddenly show "xDX Designer is in readonly mode" while 1 hour ago i could open the same project without any issue. In the output console i also ...
    sebastien.darmancourt
    last modified by sebastien.darmancourt
  • Jump to  - in a hierarchical design

    Hello Folks,   there is nothing nicer than a simple hierarchical design. Lets take a look at this simple example of a repeating block with two supbages and a signal that crosses the two pages.   Lets start...
    milostnik
    last modified by milostnik
  • How to control which xPCB Layout license is used when xPCB Layout is launched from xDX Designer?

    How to control which xPCB Layout license is used when xPCB Layout is launched from xDX Designer? https://support.mentor.com/en/knowledge-base/MG592190
    keith_christensen
    last modified by keith_christensen
  • CNS file cannot be loaded

    When I open my design in DxDesigner I receive a constraint message that reads "CNS file cannot be loaded".  Initially when I began my design this message did not appear but I then renamed the design and starting ...
    brian.misutka
    last modified by brian.misutka
  • Invoking Cross Reference from the Command Line

    EEVX2.3 : Does anybody know how to launch Cross Reference from command line (not the scout one) ?
    yde
    last modified by yde
  • What is the difference between Variantmanager Files *_MA.vwd and *_CO.vwd?

    Hi,   I'm wondering, what the difference is between this two files. In one of my Xpedition Designer Projects, Variant Manager only create *_CO.vwd Files for each Variant, in an other project *_MA.vwd Files. I ca...
    michael.weber
    last modified by michael.weber
  • Netlist name small/big letter

    Recently I created schematic that have mixed small and big letter. Example:      1) Vdet_R1      2) vdet_R1   I am using Mentor Graphic DxDesigner 7.9EE to edit the sc...
    farizul.azman
    last modified by farizul.azman
  • Renumber the ref-des in dx-designer

    How to renumber the refdes in dx-designer based on schematic page.   I need step by step procedure.
    Rapport
    last modified by Rapport