• Component search  by the part number in the FIND Menu

    olga_g
    last modified by olga_g
  • Change corner – take more than one at once

    olga_g
    last modified by olga_g
  • Plane assignment menu -  add wide view option.

    For now this menu is available only in small window that restricts the plane management . I think it would be much more convenient If we can see more layers per one screen and arrange wider columns.  
    olga_g
    last modified by olga_g
  • Option for ruling out of DRC special class rule for small trace lengths

          It is obvious, that there is no need to keep special clearance rule to such short trace. It enough to keep only default manufacturing rule (4-5 mil). So for dense boards we can get mach space by ...
    olga_g
    last modified by olga_g
  • 3D Interchange Capability

    Hi,      Is their any tutorial available to test VeSys2.0 3D Interchange Capability. Or any ppt or pdf explaining how interchange CAD data into PROE and VeSys2.0 or Vice versa.   Thanks, Gavisha
    gbellary
    last modified by gbellary
  • Back-drill data's output in Expeditionpcb

    We consider to develope a script to output back-drill data in Expeditionpcb. I initially consider to do as following   1 first let user to select all nets  which need to do backdrill for thier vias and plat...
    yu.yanfeng
    last modified by yu.yanfeng
  • PADS Layout9.1 can I put on error a Good DRC, like Orcad

    Hi, Like in Orcad Layout, when running a DRC, I can mark a DRC as GOOD DRC; can I do a same thing in PADS Layout9.1. I getting full DRC error, due to Blind Vias toward of Buried Vias: DRILL TO DRILL CLEARANCE ERROR...
    ssavaria
    last modified by ssavaria
  • A Enet Question In Expeditionpcb

      For some clock net, some of designers prefer to add a T filter to avoid EMI issues. Because other nets needed to match length with it, so it's welcomed to combine a total Enet from driver to receiver. However,...
    yu.yanfeng
    last modified by yu.yanfeng
  • Sexy PCB

    I saw this sexy picture in a pcb fab'site. This picture let me to rethink the difference between interactive routing and automatic routing. Today, Only interactive routing can make sexy pcb. When Auto router can make ...
    yu.yanfeng
    last modified by yu.yanfeng
  • How does it work when using Auto-Route to perfom rounting of T-Topology and length matching of signals?

    I have PCB design that requires the use T-Topology and length matching, so I did T-Topology rules setup using CES. for example the T-shape net or signal consist of Source to Virtual Pin, Virtual Pin to Load (in this c...
    bongani
    last modified by bongani
  • Out Of Sync in Xtreme PCB

    Hello,   I would like to know, if anybode else here in the community also has an issue with "out of sync" when joining an Xtreme session.   Usually we have two clients in a session. If a third client trie...
    Andreas.Schaefer
    last modified by Andreas.Schaefer
  • Do you need negative planes in Board Station XE?

    I am soliciting feedback regarding a change Mentor Graphics plans to make for the Board Station XE (BSXE) flow starting in BSXE2007.9.  For every release since 2007, we have emphatically stated that use of the po...
    steve_shively
    last modified by steve_shively
  • Create a perforation or a score

    Anyone,   Could someone share how to create a perforated edge or a Score to a PCB panel?  I have two separate boards that I have laid out and these two boards would always be ordered together.  It woul...
    azimmerman
    last modified by azimmerman
  • A issue about thermal ties broken with the dynamic dynamic planes

    2007.2 and 2007.7 all have issues about thermal ties broken with the dynamic planes. Some of broken will checked by hazards review,but some of broken not be checked.  Use should take care of this issue if they on...
    yu.yanfeng
    last modified by yu.yanfeng
  • Anyone have some good DDR training material?

    Our company has neglected to follow Moore's Law and now our PCB department has hit a brick wall as far as keeping up with current technology.  We are looking to implement several mDDR and DDR2 designs in the next...
    craig.myers
    last modified by craig.myers
  • Reuse and refdes...

    When I use the reuse function all my decoupling  with the same value and same net connection are placed anywhere in my reuse block. How can I avoid this? The IC U4 can have C98,C99 on the schematic but C263,C264 ...
    alherault
    last modified by alherault
  • Decrease solder mask clearance

    Hi. I think this is simple to do, but I don't know how to do it.   I have a pad that is say, 1 inch by 1 inch. When I look at the CAM file I made for the solder mask then it shows the mask over the pad, as it sh...
    kevyjones
    last modified by kevyjones
  • Can't combine 3 nets into an Enet ?

    The design is very simple,  there are 3 signal nets and 2 global signals. It's a keyin flow and it seems no error in the setting. ;; V4.1.0 %net %Prior=1 %page=0001 \DM1_VP_CLKOUT\    \D3\-\P1\ \...
    yu.yanfeng
    last modified by yu.yanfeng
  • Resoucerces from the past

    Wow, new Mentor site but old resources   Bortolo
    bbpcbdesign
    last modified by bbpcbdesign
  • Mentor will acquires Valor

    If Mentor finally take overs Valor,Tota market capacity for pcb will reach 500 million.           Enlarge font           Reduce font Mentor ...
    yu.yanfeng
    last modified by yu.yanfeng