• How to enable project file?

    I want to do forward annotation but it seems not possible due to disabled project file. Please see attached image.   Thank you.
    hbenawe
    last modified by hbenawe
  • Import PCB into New Template

    I would like to use my existing Job parameters file that contain all needed info in Xpedition Layout. This new PCB Layout was a conversion and doesn't have all my standard configs.   Overall, I'd like ...
    aiewould
    last modified by aiewould
  • FPGA Part Wizard Symbol Edit

    Hi,    I have packaged FPGA by using FPGA Part Wizard in Xpedition Library Manager. I am wondering how to edit FPGA symbols like, remove over lapping of pin names and net names etc and also pins lock t...
    joniengr081
    created by joniengr081
  • Finding Mentor Footprint of Components

    Hi,    I am wondering how to find mentor compatible footprint or cell for the following two components ?  1- SDRAM - MT41K256M16 2- Flash - S25FL127S
    joniengr081
    last modified by joniengr081
  • Finding Mentor compatible Symbol and Footprint

    Hi,    I am looking for mentor compatible Symbol and Footprint of ADS5404. Is there any database provided by Mentor to search and download the Package ?  
    joniengr081
    last modified by joniengr081
  • How to batch setup same net via to via clearance by scripts?

    Hi, all   An anylayer PCB has so many same net clearance to set, like you see below. Is there a way to batch setup by scripts? Thanks!   
    ziyu.wang
    created by ziyu.wang
  • Using VX2.6, how do we detect the height of all the SILK or SILKSCREEN used in PCB?

    I wonder if we created report writer or maybe there is an script to check the SILKSCREEN height used in the PCB.
    hbenawe
    last modified by hbenawe
  • Default/Classic Window Layouts

    We have a new user learning DxDes (XV2.1 PADS Netlist). They were going thru the eval guide and switch the layout from Default to Classic. DxDes promptly crashed, and now will crash every time they select a project (d...
    gedeakins
    last modified by gedeakins
  • DC Resistance /RLGC

    Hello Experts, Can we extract DC Resistance/RLGC of Power planes in hyper-lynx? Please do the needful. Regards, SK
    shravan.sk
    last modified by shravan.sk
  • Pads pro vx.2.6 fablink general interfaces

    Dear Sir/Madam, In pads pro vx.2.6 layout under File -> Export -> General Interfaces there is Generic ATE and several others. In pads pro vx.2.6 fablink under File -> Export -> General Interfaces th...
    grant2019
    created by grant2019
  • Pads PRO Fablink vx.2.6 html pick & place, pdf assembly

    Dear Sir/Madam, In Pads PRO Fablink vx.2.6 is it possible to generate a html pick and place file and pdf assembly file. Regards Grant
    grant2019
    created by grant2019
  • Unable to load design , The layout file is missing .lyt

    Dear All,   As I proceed with the layout, after DRC the layout suddenly stops and then I cannot open the file  I get a msg saying  Unable to open the layout ,The layout .lyt is missing  please ...
    josia_jacob
    last modified by josia_jacob
  • error occurred during EDX import.

    i'm using DxDesigner VX2.3. i created a layout cell for ICS41352 (DigiKey part number ICS-41352-ND), but after downloading i received "Error(s) occurred during EDX import. Please review log file at C:\WDIR\EEVX.2.3\ED...
    robb.zimmerman
    last modified by robb.zimmerman
  • Layer Stackup DRC

    Hi All,   In VX? the Layer Stackup DRC was introduced. Assuming Xpedition is a professional package, a total waste of effort/resources, in my humble opinion. (but who am i).   As an research Institute we d...
    charles.ietswaard1
    last modified by charles.ietswaard1
  • can't find PQ part in Library

    I am using Pad Designer for schematic capture and using the Netlist flow. I get the part from PQ and it seems to download the part. I get this message below. Problem is I can't find the part. It doesn't show in m...
    gzuk
    created by gzuk
  • DDR3 Setup and Hold Time Calculations

    Sir I am doing DDR3x Batch Simulations using hyperlynx. Upon completion of the simulations, it gives result pass and fail results and outputs an excel sheet. When I click setup tab, It expands and open up 5 columns....
    m.ather
    last modified by m.ather
  • Drag Move is very slow in PADS Logic.

    Selecting and dragging multiple objects in PADS Logic is very slow. By the way, disabling VGA makes this operation very fast.   Are there any settings available for VGA? If you disable VGA, some notebooks will ...
    ksh
    last modified by ksh
  • Code for manipulation property

    Hi All.   I am new to scripting in Dx, so a need some help for task that seems simple.   On my schematics I have a symbol/component with REFDES=_PCB (this is always the same) This component has a proper...
    peter_secom
    last modified by peter_secom
  • Not able to delete Symbol

    Hi,    I am not able to delete symbol. "Warning Cannot delete the symbol. The symbol is locked by another user" I am the only user on this computer. How to delete this symbol ? The symbol is not c...
    joniengr081
    last modified by joniengr081
  • Block Interface with multiple nets in DxDesigner

    Hi,    I am wondering how to use Bus in Block interface when there are multiple nets in the Block and they have to be connected to another Block in the top level design. Any video or any document ...
    joniengr081
    last modified by joniengr081