Hi all. There's a new press release that talks about the UMC validation of Calibre nmDRC for 65 nm. http://www.mentor.com/company/news/umcvalidatecalibrenmdrcphysicalverificationumc65nm.cfm ... The Calibre pull down menu does not show up automatically on the Cadence Schematic Viewer. I need to click on Analog Environment first, for the Calibre menu to show up. I am using 2007.3 version of Calibre and 5.1 v... There's a new paper that came out at SPIE called System to Improve RET-OPC Production by Dynamic Design Coverage Using Sign-off Litho Simulator. It's an article that talks aboiut allowing RET/OPC production sy... There's a new tech note inside the Mentor Graphics SupportNet site that talks about the available support documents for the Calibre xRC calibreview integration into the Cadence Virtuoso environment. The technote ID is... Mentor Graphics Corporation (NASDAQ: MENT) today announced it has aligned its integrated circuit (IC) implementation product lines under the Design-to-Silicon division to better address the design and manufact... Here's some information from a tech note in Supportnet that was recently published: MG242346 Symptom: When performing an inductance extraction if you encounter these errors below:... When designing in P&R environments, standard cells and IP blocks are represented as LEF cells with abstract data in them. To run Calibre DRC or LVS on a GDS file, the DEF design must be translated to GDS a... Most of the foundary provide DFM deck and all user use it blindly . Most of the time its increase are and decrease random yield Hi, Specifically, my comments will be focused on using the Calibre Interactive (GUI) for xRC but it could apply to the other flows as well. We have many users of the GUI at my company including ... TVF calibre deck line number is diffrent from reported by calibre if any bug in that line . How trace it with calibre deck I need to output ornet not to results database but as an input layer to other operations (not net area ratio...). any idea? Hello everyone. I am using xrc to do flat extraction of a reasonably small layout. It works well, but if I do full '-rcc' distributed/coupled RC extraction, the resulting netlist is large and th... hi can any one discibe me abt reflow and wave soldering and recomendation to use the same My name is Randy and I have been a designer for twenty five years with an automotive component parts supplier. We presently use a finished .2mm via in pad in 0603,0805 & BGAs. My question is what in the indu... To avoid extracting RFMOS parasitics in PEX, I used hcell file and gate level extraction type. Here is my hcell file: rfnmos1v nmosrf After extraction, I found following warnings. 1) Warning: Hcell r... Using PADS Layout 2007.2, I have created an inner layer with a mixed/split plane. That all seems fine, but then when I look at my Gerber plots, they are "hatched", and I want them to be solid. ... All, I agree completely with Pete’s comments regarding building a trusting relationship with your PCB fabricators. He also brings up another good point regarding cost, to which I pose some furth... I have started migrating projects to ee2007.2 and am losing component attributes, xref attributes, and oats values in the resulting dxdesigner schematic - any one having similar issues? I understand there is a white paper floating around that covers delay formulas and provides syntax examples for different topologies. Does anybody know where I can find one? Unfortunately, I don't know the Author. ... I need to get DRC error when the total area of polygons for a layer is greater than x micron square. Any idea?