Log in to create and rate content, and to follow, bookmark, and share content with other members. Hi Can we use for loop or foreach commands after "OR" command in tvf? Example: I want to implement below svrf command using tvf. MYOBJ = OR M0_DRW M1_DRW M2_DRW M3_DRW I have tried below... Hi, How can we translate a particular text labels by its net name. Example: If we want to translate the all vss labels as a calibre gdsii output, how can we implement this. Thanks and regards Pulakanti S... Hello All, I am new to calibre and I am facing a problem about "missing inductor" and I have been trapped for a while. At the very beginning, I was about to build a basic LC based bandpass filter layout. When I pass... Hello, I am writing some DRC code that I want to output markers for all pins that are on the boundary of the design layout. The boundary has its own layer that is a rectangle that fills the entire design, so the edge... I would like a simple check to highlight nets which connect only to gate(s) (n and/or p) and only ntype S/D diffusion. I am not sure which way to address it When using the packager command on DxDesigner VX 2.1, I receive the message "Cell Name 'C1210_2.7' is not a valid cell for Part Number '453564145041'". What does that mean? And what is a Cell name? Thanks Is there a way to automatically exclude parts (such as Mounting Holes and PCB-decals) from the placement file? In the PADS Databook, I have set the property "Part List exclude" to value "True" for certai... I'm trying to select a net and run Field Solver to get the trace capacitance and delay values from each net. But I can only do that for each small segment of the entire net. Is there a way I can select the entire net ... We're working on an addin in c# that results in a DLL that is launched on startup. However, this requires some custom code and installation on the user's desktop.As we deploy more cloud infrastructure, our IT organiza... I'm working on a C# plugin that will count the number of connections in xPCB Layout and generate a report similar to Output -> Design Status. However, I can't seem to get the same connection count as desi... I'm hoping to find a solution to using the LVS black box statement in Calibre with PCells in Cadence. For my application I'm making some novel test structures that LVS normally considers to look like a few transistor... I use Default Pan and Zoom setting, but the scroll speed is too low, so how can I make it faster? Should I change Windows scrolling settings or maybe there is an option to set scroll speed only for Xpedition Designer? I am wondering how to tune one signal in LVDS pair ? The "Interactive Tune" option tune both LVDS signals while the option "Manual Saw Tune" can tune only one signal in LVDS pair with saw pattern but what I am looking... I only have a couple of screenshots but no more information about this tool. Has anyone heard of this? Can anybody explain to me how create and use and where store a logical-physical reusable block in PADS Pro Flow? is there a way to get more spacing between the crossrefs when they wrap? We are currently running Xpedition VX2.4; but not using EDM flow. We are not able to connect our DX Central library with Oracle Cloud through Oracle client. Just like connectivity in between Central Library with ... ...... . (from task manager)..i have to kill the process in TM after this. . . . ALE will open the LMC if i open it 1st in the library manager tool and the "connect" to it with ALE.. Does this imply that ALE is... How to see every occurrence of a Calibre DRC error throughout the design https://www.youtube.com/watch?v=Pwz-jNkCq5Y I watched your video on youtube and found these settings in my environment. However, I am ... Is there a Viewer available for PADS Pro Designer and PADS Professional Layout files?