How many transistors are in the parasitic extraction netlist?

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    Is there a way to find how many transistors are in my design from the parasitic extraction netlist?


    In a flat PEX run, which is accomplished by not defining any hcells or xcells, or by giving an empty hcell and xcell list,

    all transistors in the design will be represented flat as explicit "m" devices.

    i.e. there will not be any devices within any subckts and so there will be no problem of determining how many subckt instances there are, for example.

    In this case a grep of the form:

          grep -i ^m | wc

    will provide the number of "m" devices in the Hspice netlist in the flattened design.

     

    If a PEX run with Calibre xRC is done using xcells, in either a gate level or a full hierarchical extraction,

    then the data is more complex as you will have all the subckt instances to assess as well.

    Calibre xRC does not give a device count in any log file,

    however, you can turn on these switches to get more information reported in the stdout log:

          calibre -xrc -fmt    -fmt_warnings  -fmt_info   rulefile >&! fmt.log

     

    The LVS report file gives device counts after transformation on a per cell basis.

    Please consult these related TechNotes for more information:

       MG250616 Using Calibre Query Server to get a total flat device count from a hierarchical netlist

       MG38181   How to report number of transistors and their total gate areas in Calibre DRC