Q1: How do you setup parallelism rules through Constraint Manager?
You can create them from the Noise Rules tab (View > Tabs > Noise Rules) or from Edit > Parallelism Rules > Define Parallelism Rules. After creating them, you will need to assign them between nets or Constraint Classes. Please note that parallelism rules are not used by Interactive Routing or by Auto Route – they only come into effect during Review Hazards.
Q2: Do parallelism rules carry over into constraint templates?
Yes, constraint templates can capture all constraints defined for a specific net.
Q3: For the new Power Net constraints, where do violations appear? In HyperLynx PI’s DC Drop results, or the ‘Review Hazards’ dialog window in xPCB Layout?
The violations appear in HyperLynx PI’s DC Drop results. The constraints are imported as maximum current & voltage drop values – in the Batch results, measurements greater than these values are reported as errors.
Q4: Can Phase Tolerance constraints be set between two points on a differential pair? In other words, instead of running from driver pin to receiver pin, can we stop just short of the receiver pin so some phase mismatch is tolerated in the “last mile” of the route?
No – the constraints apply to the entire electrical net. You probably want to take a look at the ‘Convergence Tolerance Max’ and ‘Distance to Convergence Max’ constraints which control the “last mile” of the route.
Q5: How can we copy a stackup from one design to the next? It would be nice if Stackup Editor had some sort of tool to import A .STK file.
This is planned for VX.2 – check the BSD Release Schedule. In the interim, you can set up a Layout Template in xDM Library Tools which can be imported into front-end Constraint Manager through File > Import > Layout Template (before any back-end data exists).
Q6: Do Phase Tolerance constraints cover the entire electrical net? For example, if I have serial resistor, will the constraint cover from driver to pin 1 of the resistor, or will it cover driver to receiver?
This depends on how the electrical nets are defined. By default, you should have two differential pairs right now - one pair before the resistor, and one pair after the resistor. Each of these diff pairs maintains its own Phase Tolerance constraint, distinct from the other.
If you enable the ‘Series’ checkbox under the ‘Parts’ tab for these two resistors, you can re-create the differential pair so it covers from driver to receiver (ignoring the series resistors in the middle). This single differential pair will maintain a single Phase Tolerance constraint from start to finish.
Q7: Why would someone use Constraint Manager versus Constraint Editor?
Constraint Editor is more of a context-sensitive individual editor – when you want to manage constraints for the entire design, the full standalone application is needed.
Q8: Does Stackup Editor’s 2D field solver account for gaps in the reference plane? In other words, I have traces on Layer 3 going over a ground plane with a large gap, so that it actually references Layer 7. . . does Stackup Editor account for this?
In HyperLynx 9.0 and later this is accounted for by the field solver and the impedance discontinuity is modelled. However, the planes in Stackup Editor are assumed to be uniform and continuous.
Q9: How can I add Z-axis ‘Plane to Plane’ clearances?
This has been submitted as Mentor Idea D7620 – use the link to vote for this enhancement.
In the meantime, you may find the ‘Plane Shadow Voids Generator’ script in AATK useful. This script creates a plane void underneath via & surface mount pads for a specific net or Net Class. The shape of the void is derived from the pad geometry, and you can place voids on any number of layers above or below the pad.
The voids are static, so if you make changes to layout you must select the nets you previously ran the script on and regenerate the voids. However, you can select multiple nets to run which makes replacement an extremely quick process.
The script may be found in under AATK > Flip Chip > MISC > Plane Shadow Voids.
Q10: How do you display Phase Tolerance in nanoseconds (rather than length)?
Change the ‘Type’ column in the spreadsheet from ‘Length’ to ‘TOF’.
Q11: Why would I use Differential Pair Tolerance over Differential Pair Phase Tolerance?
If you are using Differential Pair Phase Tolerance, there is virtually no need to ever use Differential Pair Tolerance. By keeping the legs dynamically matched at every point between driver and receiver, you guarantee that the lengths will match at the receiver end. Phase Tolerance supersedes Pair Tolerance in this way.
Q12: Does the Power Net Supply Voltage get applied in HyperLynx?
Yes, it will apply the correct supply voltage within the Setup > Power Supplies dialog in BoardSim.
Q13: How do you put a serial resistor in an electrical net?
Use the ‘Series’ column under View > Tabs > Parts to control whether a components should be considered in splitting the electrical net or not. If the checkbox is disabled, the tool will split the electrical net. If the checkbox is enabled, the tool will ignore the series component and maintain the electrical net through it.
The default behavior is controlled by recognizing reference designators on the resistors – make sure Setup > Settings > Discrete Component Prefixes is configured correctly.
Q14: Is there a way to take into account Pin Package impedance into account with the Field Solver?
This is something that can be specified within an IBIS model and simulated by HyperLynx, but Constraint Manager is not equipped to do this. However, you can specify Pin Package lengths which will be considered in length matching & tuning.