I've been working with an evaluation copy of VeSys for a week, and right now I'm stating to do real work with the licensed version. I've done the test drives and read through the documentation, but have not (yet) received training. The software is more or less self-explanatory, however some questions have remained open. I hope it is ok to bring them up here before my official training course...
1. We are doing aircraft harnesses and are dealing with lots of variants and optional equipment. For a example, a customer might select from a variety of navigation equipment and instruments according to national requirements. Of course, we only want the required wiring in the aircraft and produce accurate documentation for each variant. We want to move optional equipment and associated wiring into separate schematic pages and depict the interface to the aircraft as off-page references. Is this the right approach? Will VeSys handle
2. How can we add an overbraid to a completed wiring bundle (and splices and shield termination) without the tedious process of defining a dedicated multicore in the library each time? We need a clean separation between electrical design and manufacturing (VeSyS Design and Harness), so adding the overbraid in VeSys Harness is no option.
3. Some devices come with a short length of wiring and a connector already installed to the end of it. We could of course treat this as a "black box" and just draw the mating connector in the harness. While not absolutely necessary, it would be more accurate to define a device with the wiring, the colour codes of the wiring and the connector so the physical setup shows up in the documentation. Is this possible in VeSys?
4. While defining drawing borders, I had lots of trouble with the automatic zone areas. Everytime I define columns and rows, the paper format is changed to a very large size. Is this a bug?
5. We often have to attach multiple ring terminals to one stud. Also, sometimes multiple wires will have to be crimped into one ring terminal. How does VeSys handle both cases?
6. It is common practice here to allocate a wire number to a multicore as a whole, not to individual wires of a multicore. This prevents manufacturing from exposing the inner conductors of shielded wires just to attach a label. Discrimination of inner conductors is done by colour code, only. Can VeSys be configured to automatically handle this?