In Plane Noise Simulation How to Calculate AC Model for IC Pins,Can you Explain in brief
Well this is a very good question that unfortunately can’t be answered briefly. Actually the AC model shouldn’t be calculated (it would be too complex) but simulated into a full system simulation bench that is made of die and package driver/receive PDNs along with the PCB’s PDN. The current flow is different for various systems depending on the IC stage and technology involved. For example the current flow is different if you are looking at an IC core, a pre-driver stage or an IO stage. It is also different if you look at a single-ended interface vs. a differential bus. For a single-ended interface the termination scheme will make the difference.
If you have IBIS models for your drivers and receivers you can use in LineSim a black box symbol instead of the regular built in symbols and then you can expose the supply pins through and I/O buffer element (B-element in HSpice, _IO_ element in ELDO). The Spice statement power=off will enable the Spice engine to simulate the current drawn from the power supply and if you add to this circuit all the non-idealities like package parasitic, power supply output inductance/resistance and the PDN impedance (S-parameter) then you will be able to get a better representation of the AC current at any location. You will need also the right stimulus pattern to get even closer. Don’t forget that the currents flow in loops, so the return paths should be included into this picture. Typically this is done by using S-parameter models that have ports for both power and signal nets. That would also include coupling between TLs and PDN.
For core logic PI analysis usually the concern is when the system wakes up or goes to sleep, so step pulses would be good enough.
This is in a nutshell how you can find the shape, amplitude, rise/fall times and any other parameters for your AC Models, but again there is much more to be explained.
can give me an simple example of this one then it`s clear for me
First of all let’s clarify that for a core logic or pre-driver stage the current distribution is confined into a small region underneath the chip. The current will flow from power supply to ground pins, so TD or FD co-analysis of the chip, package and PCB would be enough.
However for I/O stages the current distribution is not localized anymore and it involves the driver, the receiver and the channel that links them. In single-ended interfaces, the drivers are usually push-pull while for differential interfaces they are current-steering.
For simplicity we can take a simple example of a push-pull driver and its associated receiver connected by a transmission line. To simplify even further this setup, we can replace the receiver by its input capacitance. We can also add parallel terminations to mimic the ODT behaviour.
In the case when the ODT is off and the input stimulus is logic low the current will flow from the transmitter’s power supply pin through the pull-up transistor, TL and it will charge the input capacitance of the receiver (the push-pull driver is an inverter). When the input stimulus changes its value to logic high, the pull-up transistor is turned off while the pull-down transistor is turned on. The input capacitance of the receiver is now discharged through TL and the impedance of the pull-down transistor. The two transistors might be on at the same time for a small period of time and that will give rise to an unwanted current that flows from the power supply pin directly to the ground pin. This current is called crow-bar current. Typically this configuration is called voltage mode.
If the ODT is on, then the pull-up current will flow from the driver’s power pin through the pull-up transistor, TL and pull-down resistor to ground. The pull-down current will have an opposite direction and will flow from the receiver’s power supply through the pull-up termination resistor, TL and pull-down transmitter transistor to the transmitter ground pin. The shape of the pull-up and pull-down currents will be different depending if the stimulus contains transition or non-transition bits. There will be return current that will flow through reference planes even before the signal reaches the load, due capacitive coupling between TL and its reference planes. The high-speed current flow will follow the signal trace due to proximity effect. Typically this configuration is called current mode.
For differential signals the story is slightly different since there is no net current change from power supply. This is why we do not worry about SSN in differential systems.
I have attached for you a very simple LineSim setup along with corresponding models that will allow you to visualize the signal and power/ground currents for a single ended DDR3 DQ line. You will need Hspice to be able to run the simulations. The setup can be modified to make it work in ELDO as well. You can toggle between oscillator and PRBS stimulus by editing (comment out) the stimulus file. The top topology uses an ideal power supply, while the bottom topology contains an S-parameter model extracted from PDN. You can add/remove more details to this setup at your wish. I have also attached a screenshot of the waveforms that show the signals and power/ground currents for the two cases ideal vs. non-ideal PDN.
If you go to at the link below you will find lots of good documents explaining in detail the SI/PI co-simulation process, modeling techniques and the industry trend:
For additional details about LineSim usage applied to this type of simulations, you can have a look at Mentor’s AppNote 10839.
Hope this helps.
I thank you very much for your model. I was trying to simulate in your model to understand the concept you explained here but it results in an error. Could you help me out with that please.
Thanks and Regards,
The simulation deck that I have provided runs without errors if you use HSpice instead of ELDO/ADMS as Spice engine. If you don’t have HSpice you will have to do several modifications in order to make it work with ELDO and perhaps Mentor folks are better positioned to help. Few differences that I am aware of are:
If you want to better understand the concept I would suggest you to read my U2U presentation from May 2012, Waltham, MA:
I am also attaching a simple simulation deck that you can run with ELDO/ADMS and that might provide you a starting point in this area.
I thank you very much for your kind reply. I have gone through your slides and the program you gave and I really enjoyed them.
I am a student trying to learn PDN AC analysis in Hyperlynx. Could anyone of you kindly help me to do decoupling analysis for my application mentioned in the attached excelsheet?
Any examples or references or hints are highly appreciated. I thank you in anticipation.
There is plenty of good documentation that you can use to improve your knowledge in the area of PDN analysis. I would suggest you here only few websites to visit:
Specifically for some of your questions you can read the sample chapter of the Power Distribution Design Methodologies book and you can download the Microsoft Excel demo file that calculates the frequency – domain response of single and multiple bypass capacitors that you can find under the tool download area..
I hope this helps,
Thank you very much for your suggestions and resources. I think I have got a nice entry point.
Hallo Everyone and Cristian,
Could you also please give some suggestions to the following problem. How to model for Analog rails in Hyperlynx? Please find the attached screenshot of the situation.
Here, we have ferrite beeds between the source and load. How to do decoupling analysis with a ferrite beed. Any example would be highly appriciated.
Thank you very much in advance.
If you are interest see the total effect of your filter network, just create a subckt model for the fiter circuit, and assign this model one of capacitor , which connected to the power. However, the tool is targeted to Power plane analysis, fanout'effect. For power filter circuit analysis, you may need Hyerplynx analog.
The practical way to analye the performance from VRM to the load point in Hyperlyn is that you first export a PDN model, and re-create total topology in Linesim.
Thankyou very much for your kind reply. I understand that you recommend me to model the filter network as RLC and assign that model to a capacitor which is connected in series to the VRM?.
As I am newbie to the Hyperlynx simulations I would be very glad to see an example where one creates the total topolgy of an exported PDN model (Simple model). I think method gives the designer more degrees of freedom to analye the PDN.
Thankyou once again for your inputs. I would like to share the solution over here.
I'm also a student like you and I have the same trouble with you as the 'PDN _Analysis' excel lists. I want to ask you if your problems have been solved? Would you like to share the answers with me？The question of how to set up AC model and how to choose the signal type in stimulus are my major concern. When I run ‘Distributed Analysis ’, some power pins I can't observe because its reference layer is not available. I don‘t know how to set reference net. Is there anything wrong in my PCB? My PCB has 6 layers，including two ground planes but no power plane.
Could you please explain me how to extract S-Parameter (S2P) model from PDN as in your above example (Test_case)?.
Why did you use voltage source "V 3 2 0.2314V" in SPICE_WR.sp file to load S-Parameters file?
Please see the link to the attached AppNote from Mentor that explains in detail how to export S-parameter Models from a board PDN.
In regards to the second question, about the voltage source that was to compensate for an error that I made on an earlier test and it is not needed if the S-parameter is properly extracted (the VRM should be removed from the PDN during the extraction phase, so we don’t double count for it). The S-parameter model should approach 1 and contain enough data points at low frequencies to enable the simulator to extrapolate the DC value.
I thank you very much for your kind reply. Could you also please help me with one more issue.
Based on your examples and study material I have written an IBIS file for an IO buffer "DQ_FULL_ODT50_533" using an IBIS file from Micron "u68a_at.ibs", please find it in attachments. I am not able to make it work. Could you go though "DDR2_MemCtrl_DQbus.cir" file from the attachments and give me some suggestions?. I guess that the problem lies with the ground and power clamp definitions which are not there in IBIS file from Micron?
Or I can already use hspice files given by Micron instead of IBIS files in this case I think?. Any further thoughts on this are highly appreciated.
You need to change “Ven enable 0 0” to “Ven enable 0 1” as your driver is active high. Please see the modified files in attachment.
Thank you very much for that. I overlooked that point.
Referring to your presentation slides on co-simulations,I think you used current mirrors to maintain same current across all data lines?
Assuming that all the DQ topologies are almost identical, the current profile will be similar, so we can multiply the current that flows through one line by the total number of lines. This technic speeds-up the simulation without compromising the accuracy and is very useful especially if the driver models are transistor-level Spice models. If you want to include the address, command and control signals, you will need a current mirror for each topology that is different or in other words each time when the current profile changes.
Yes, exactly. My aim is to include also address and control signals into the schematic along with data signals to extract AC model for the IC pins and also do noise simulation.
Actually, I have "heavy point to point and T" topologies implemented for data and address buses. So I have segregated the similar DQ and Ax lines seperately based on your above comment.
So, in this situation I think I use current mirrors?. Do I use these current mirrors only in simulations? because there are no current mirrors on actual board?.
Can I use Current mirror like this below?
VDD VDD 0 DC 1.8
Vo Vo 0 DC 0
R1 VDD VGS1 200k
M1 VGS1 VGS1 0 0 N_1u L=2 W=10
M2 Vo VGS1 0 0 N_1u L=2 W=10
Thankyou very much,
The voltage and current control elements are not modeling any physical component on the board, but they are used for various simulation purposes. As you see I used a couple of current- controlled current sources on my presentation (green color) just to be able to measure the currents. When you use Spice models in your LineSim schematics, the current probes get grayed out so you can’t sense the current directly. This is a workaround the limitation…
I will let you now discover more by yourself.
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