4 Replies Latest reply on Mar 19, 2013 9:50 PM by kbmani

    Via modeling - 3D

    kbmani
    kbmani Mar 15, 2013 4:24 AM

      Hi,

       

      In hyperlynx 8.2.1, via modeling is possbile using 3D EM solver. It is allowed if the via is connected between two layers.

       

      If I have a via with three ports ( one to the top, 2nd one to an inner layer and 3rd one to bottom), 3D EM is not possible.

       

      Does it mean 3D is not possible if I use a standard via ?

       

      Please explain the reason behind this.

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        • 1. Re: Via modeling - 3D
          cristian.filip
          cristian.filip Mar 15, 2013 10:40 AM (in response to kbmani)

          Hi,

           

          3D EM modeling of the vias is usually for high speed signals running at speeds above 3GHz. Those are in general point-to-point differential topologies and I can’t see many cases where someone would want to have three ports on a via. Could you provide an example, where you need this feature?

           

          Cristian

          • 2. Re: Via modeling - 3D
            yu.yanfeng
            yu.yanfeng Mar 15, 2013 5:04 PM (in response to kbmani)

            For arbitary via modeling, you can use Hyperlynx 3D EM(IE3D)~

            yanfeng

            • 3. Re: Via modeling - 3D
              kbmani
              kbmani Mar 18, 2013 9:36 PM (in response to cristian.filip)

              Hi,

               

              Thanks for your reply.

               

              How can we make a standard via which can connect a signal from the top layer to an inner layer ? But the via has to be extended ( i.e. via stub) to the bottom layer.

               

              Again, I know very well that 3D EM modeling of the vias is usually for high speed signals running at speeds above 3GHz. But I would like to know in what way does it improve the accuracy? or....why is it prefered for high frequency simulation?

              • 4. via properties- no of layers
                kbmani
                kbmani Mar 19, 2013 9:50 PM (in response to kbmani)

                Hi,

                 

                In hyperlynx, after placing the via in the schematic, when I right click , following options are available.

                 

                Connected layers:

                 

                edit

                 

                view.

                 

                If I keep the connected layer = 2 and set the layer span from top to layer 3, then the via is connected from the top layer to the layer 3. i.e. it is not a standard via ( via from top to layer 3 and via stub from layer 3 to bottom layer).

                 

                If I want to make it as a normal standard via, then I have to assign the connected layers = 3. Layer span: Top to bottom.

                 

                after clicking the OK, 3 ports are visible in the via. The middle port can be connected to a txn line which is connected in any inner layer.

                 

                Is this the right way to make a standard via in hyperlynx linesim?

                 

                When I assign this way to make a standard via , I am not able to use the option " 3D EM modeling".

                 

                Please correct me and guide me.